3,043 results on '"Integrated circuits -- Intellectual property"'
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2. Researchers Submit Patent Application, 'Semiconductor Structure Including Capacitor And Method For Forming The Same', for Approval (USPTO 20250016982)
3. Researchers Submit Patent Application, 'Self-Aligned Structure and Method on Interposer-based PIC', for Approval (USPTO 20250012983)
4. Researchers Submit Patent Application, 'Method For Stacking Integrated Circuit Wafers And Dies', for Approval (USPTO 20250015045)
5. Researchers Submit Patent Application, 'Method For Producing A Package For A Semiconductor Chip, Package For A Semiconductor Chip And Semiconductor Device', for Approval (USPTO 20250014970)
6. Researchers Submit Patent Application, 'Integrated Power Device With Energy Harvesting Gate Driver', for Approval (USPTO 20250015707)
7. Researchers Submit Patent Application, 'High-Voltage Gate Driver Integrated Circuit Using Galvanic Isolator', for Approval (USPTO 20250015077)
8. Patent Application Titled 'Semiconductor Integrated Circuit, Semiconductor Device And Method For Aligning Semiconductor Integrated Circuits' Published Online (USPTO 20250015012)
9. Patent Application Titled 'Semiconductor Device Structure Including Fuse Structure Embedded In Substrate' Published Online (USPTO 20250017002)
10. 'Semiconductor Device And Method For Making Same' in Patent Application Approval Process (USPTO 20250015066)
11. 'Nonvolatile Memory Devices And Memory Packages Including The Same' in Patent Application Approval Process (USPTO 20250014645)
12. 'Integrated Circuit Memory Devices Having Highly Integrated Memory Cells Therein With Enhanced Landing Pad Structures' in Patent Application Approval Process (USPTO 20250016981)
13. 'Integrated Circuit Memory Devices Having Enhanced Memory Cell Layouts' in Patent Application Approval Process (USPTO 20250016991)
14. Researchers Submit Patent Application, 'Semiconductor Packages With Multiple Types Of Conductive Components', for Approval (USPTO 20250006585)
15. Researchers Submit Patent Application, 'Method For Improving Fdsoi Device Leakage', for Approval (USPTO 20250006743)
16. Researchers Submit Patent Application, 'Double-Sided Polishing Of Semiconductor Wafers With Dynamic Control', for Approval (USPTO 20250001546)
17. Researchers Submit Patent Application, 'Double-Sided Integrated Circuit With Damage Sensor', for Approval (USPTO 20250006629)
18. Researchers Submit Patent Application, 'Component Having An Integrated Converter Layer And Method For Producing A Component', for Approval (USPTO 20250007237)
19. Patent Application Titled 'Semiconductor Packages With Multiple Types Of Conductive Components' Published Online (USPTO 20250006685)
20. Patent Application Titled 'Semiconductor Packages With Multiple Types Of Solder Balls' Published Online (USPTO 20250006682)
21. Patent Application Titled 'Semiconductor Package' Published Online (USPTO 20250006625)
22. Patent Application Titled 'Semiconductor Package And Method For Identifying Integrated Circuit Layers In Stack' Published Online (USPTO 20250004045)
23. Patent Application Titled 'Electrostatic Discharge (Esd) Protection Circuit Including An Avalanche Semiconductor Controlled Rectifier (Scr) With Parallel Connected Static Trigger Control Circuit (Tcc)' Published Online (USPTO 20250006724)
24. 'Semiconductor Package With Retreating Metal Layers' in Patent Application Approval Process (USPTO 20250006607)
25. 'Semiconductor Device' in Patent Application Approval Process (USPTO 20250006604)
26. 'Double-Sided Integrated Circuit With Electrostatic Guard Ring' in Patent Application Approval Process (USPTO 20250006663)
27. Researchers Submit Patent Application, 'Semiconductor Package', for Approval (USPTO 20240421125)
28. Researchers Submit Patent Application, 'Semiconductor Integrated Circuit Device', for Approval (USPTO 20240421089)
29. Researchers Submit Patent Application, 'Integrated Circuit Workload, Temperature, And/Or Sub-Threshold Leakage Sensor', for Approval (USPTO 20240418770)
30. Researchers Submit Patent Application, 'Semiconductor Device And Method Of Forming The Same', for Approval (USPTO 20240422958)
31. Researchers Submit Patent Application, 'Inverted Gate Cut Region', for Approval (USPTO 20240420959)
32. Researchers Submit Patent Application, 'Integrated Thermal Bridges On Wirebond Assembled Integrated Circuits For Heat Spreading', for Approval (USPTO 20240421092)
33. Researchers Submit Patent Application, 'Fpga Wide Barrel-Shifters Implementation Using Packed Dsp Multipliers', for Approval (USPTO 20240419446)
34. Patent Issued for Surge protection in semiconductor integrated circuit and semiconductor memory device (USPTO 12170440)
35. Patent Issued for Microprocessor with a time counter for statically dispatching extended instructions (USPTO 12169716)
36. Patent Issued for High voltage MOSFET device with improved breakdown voltage (USPTO 12170329)
37. Patent Application Titled 'Semiconductor Devices With Different Gate Dielectric Thicknesses' Published Online (USPTO 20240421209)
38. Patent Application Titled 'Semiconductor Device And Method Of Forming The Same' Published Online (USPTO 20240421184)
39. Patent Application Titled 'Reduction of Air Gaps in FinFET Structures' Published Online (USPTO 20240420998)
40. 'Semiconductor Package' in Patent Application Approval Process (USPTO 20240421143)
41. 'Recess Poly Esd Diode For Power Mosfet' in Patent Application Approval Process (USPTO 20240421147)
42. 'Electro-Photonic Transmitter And Receiver Integrated Circuits (Chiplets) For Co-Packaged Optics And Methods Of Operation' in Patent Application Approval Process (USPTO 20240421909)
43. Researchers Submit Patent Application, 'Multilayer Moisture Repelling Films For Front End Fet Applications', for Approval (USPTO 20240413098)
44. Researchers Submit Patent Application, 'Heat Radiation Devices', for Approval (USPTO 20240413053)
45. Researchers Submit Patent Application, 'Memory Structure', for Approval (USPTO 20240412772)
46. Patent Application Titled 'Semiconductor Memory Devices Having Enhanced Sub-Word Line Drivers Therein' Published Online (USPTO 20240412773)
47. 'Contact Assembly For Power Semiconductor Chips And Power Electronics Module' in Patent Application Approval Process (USPTO 20240413119)
48. Researchers Submit Patent Application, 'Semiconductor Device With Esd Protection Structure And Method Of Making Same', for Approval (USPTO 20240405015)
49. Researchers Submit Patent Application, 'Integrated Circuit With Supply Voltage Detector', for Approval (USPTO 20240405538)
50. Patent Application Titled 'Semiconductor Integrated Circuit, System On Chip And Electronic Device To Implement Them' Published Online (USPTO 20240405011)
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