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This letter proposes a millimeter‐wave dual‐polarized (DP) end‐fire frequency scanning antenna utilizing low temperature co‐fired ceramic (LTCC) technology. The antenna features DP radiating elements, each comprising a quasi‐Yagi antenna for horizontal polarization (H‐pol) and a pyramidal horn antenna for vertical polarization (V‐pol). These elements are excited via a mode‐composited transmission line (MCTL), integrating substrate integrated coaxial line (TEM mode) with substrate integrated waveguide (TE10 mode). To mitigate phase imbalances between polarizations during beam scanning, a delay line is embedded in each quasi‐Yagi element, ensuring consistent scanning ranges for the two polarizations. Furthermore, the implementation of amplitude weighting in the feeding networks contributes to the enhancement of antenna efficiency. A 1 × 8‐element prototype was fabricated and its performance is assessed. The results show closely matched beam scanning ranges for the two polarizations (±28° for H‐pol and −30° to +34° for V‐pol) across the 26–29 GHz frequency band, with a measured maximum peak gain exceeding 9.2 dBi for both polarizations. The proposed design emerges as a promising candidate for compact mmW frequency scanning front‐end antenna systems. [ABSTRACT FROM AUTHOR]

This paper presents a novel dynamic bias latch‐type comparator combined with a voltage‐controlled delay line (VCDL), designed specifically for low‐power and low‐noise applications in high‐speed analog‐to‐digital converters (ADCs). The incorporation of the VCDL precedes the dynamic bias amplifier in the proposed comparator, thereby achieving a balance between energy efficiency and high‐speed operation. This innovative design enhances the input common voltage of the dynamic bias amplifier through the utilization of the VCDL, surpassing that of a conventional dynamic bias comparator. Furthermore, it demonstrates increased adaptability in technology scaling and efficient operation at lower supply voltages, leveraging inverters and other simple cells. The proposed comparator in 28 nm process technology achieves a 309.7 µV input‐referred noise while consuming approximately 145.8 fJ and completing comparisons in 125 ps with a 0.9 V supply and a 0.45 V input common‐mode voltage. [ABSTRACT FROM AUTHOR]

This paper proposes a digital delay locked loop (DLL) with a monotonic delay line (DL). This DLL adopts the calibration mode to reduce the non‐monotonic effects for the coarse‐tuning delay line (CTDL) and the fine‐tuning delay line (FTDL). The calibration mode detects the delay time of the delay unit, the timing resolution of CTDL, to adjust the delay range of the FTDL. Thus, the calibration mode can limit the overlap range of the delay time between the CTDL and the FTDL. The proposed DLL was implemented using a 0.18‐μm CMOS process, and the RMS and the peak‐to‐peak jitters of the DLL were 0.21% and 1.72%, respectively, at 560 MHz. [ABSTRACT FROM AUTHOR]

This paper proposes a small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit. By adopting the proposed delay unit containing a pre‐charge transistor, half cycle delay line can accurately generate half‐cycle delay, thus ensuring that the circuit can achieve duty cycle correction with small area and low power. To achieve high‐precision clock synchronization, the proposed de‐skew circuit utilizes a high‐resolution two‐stage digital control delay line to eliminate the additional clock skew between the input clock and output clock of the circuit. The test chip is fabricated in 130 nm CMOS process and the area only occupies 0.009 mm2. The chip testing results show that duty cycle correction error is within 3.2% and phase error is less than 16 ps when input duty cycle from 20% to 80% at the frequency range from 380 MHz to 1.25 GHz. And the proposed circuit only consumes 3 mW when supply voltage is 1.2 V and clock frequency is 1 GHz. [ABSTRACT FROM AUTHOR]

This Letter proposes a reliable and lightweight key generator based on a novel bit-self-test arbiter physically unclonable function (BST-APUF). The BST-APUF adds a delay detection circuit into a classical APUF to automatically test the delay deviation that produces each bit of the PUF response and generates a reliability-flag for each response to indicate its reliability. The key generator collects robust responses and produces a secure key using a cryptographic entropy accumulator. FPGA implementation results show that the overhead and the helper data length of the authors proposed key generator are significantly lower than that of the state-of-the-art schemes when generating a 128-bit key with a bit error rate of 10−9. [ABSTRACT FROM AUTHOR]

Optical digital-to-analogue (DA) conversion has the potential to realise fully-transparent optical communication systems, as it is considered to be fundamental in the most of operations, including packet switching and label processor. However, most DA converters have been confined to on-off keying modulation as opposed to phase-shift keying (PSK) modulation. In this Letter, the author provides an optical DA converter for binary PSK (BPSK) signal. The proposed scheme converts a digitised information into an optical intensity by using delay line interferometer and balanced photodetector. The scheme generates a quadrature PSK (QPSK) signal from two BPSK signals, then, the generated QPSK signal is coupled with a u-shifted signal. The four constellations of the QPSK signal are converted into four levels at equal intervals when the angle u is set at 63.4° and 26.6°. It is concluded that the optical 2-bit DA conversion is experimentally demonstrated for BPSK signal at 10 Gbps. [ABSTRACT FROM AUTHOR]

A new all‐digital delay‐locked loop (ADDLL) using successive‐approximation register (SAR) control scheme is presented. The proposed circuit architecture can effectively perform the per‐bit acquisition within one clock cycle. Therefore, the divider for generating internal SAR clocks can be further removed to achieve fast‐locking capability. Meanwhile, the harmonic‐locking problem that often occurs in a wide range of operating frequencies is also eliminated. The test chip is designed and verified with CMOS 0.18 μm technology. The measured acquisition cycles for all operating frequencies (100–800 MHz) are constant as 11 when a 10‐bit digital‐controlled delay line is employed. The rms/peak‐to‐peak jitters at the highest and lowest frequencies are 0.775/5.73 and 1.08/8.27 ps, respectively. The chip core occupies an active area of 0.015 mm2 and consumes 9.4 mW at 800 MHz. [ABSTRACT FROM AUTHOR]

A 266–2133 MHz phase shifter is proposed for LPDDR4X interface, utilising an all‐digital delay‐locked loop (DLL) and a triangular‐modulated phase interpolator (PI) to improve the jitter and linearity. The DLL consists of two kinds of DLLs: a global DLL to assist fast locking; and a local DLL which uses an adaptive‐window phase detector and a folded delay line to reduce jitter and improve linearity. The PI uses a triangular‐modulated clock waveform to achieve good linearity over a wide frequency range. The prototype chip is implemented in a 65 nm CMOS process. The measured jitter of the DLL is 3.08 psrms/19.93 pspp at 2133 MHz. The measured differential non‐linearity of the phase shifter is <0.91 LSB at 2133 MHz, and the power efficiency is about 2.7 mW/GHz. [ABSTRACT FROM AUTHOR]

Designs that operate at sub‐threshold voltages are a promising response to the ultra‐low power demands of many modern applications with relaxed performance requirements. Towards this approach, a pass‐transistor‐logic‐based programmable delay line (DL) circuit is presented that is designed specifically for sub‐threshold operation. Compared with the commonly used design, the DL consumes 79.2% less dynamic energy, 83.5% less leakage power, 47.2% better linearity across codewords, 58.6% smaller active area, and with similar resiliency to variations across Monte Carlo simulations. [ABSTRACT FROM AUTHOR]

The loop‐handover (LHO) technique is proposed to overcome the problem of close‐loop performance in digitally controlled single‐inductor multiple‐output dc–dc boost converters during start‐up. The presented technique utilises an existing clock source and requires only a small number of blocks. It also occupies a smaller silicon area, thus consuming low power and increasing efficiency. The presented technique is validated with proposed on‐chip digital controller with multiple‐output boost converter architecture using segmented delay line digital pulse width modulation. Experimental results show a successful close loop with reduced transients by using the simpler LHO technique. [ABSTRACT FROM AUTHOR]

A novel THz-wave autocorrelator consisting of an optical delay line and high-speed photodiodes was proposed for the measurement of optical waveforms with a high rate of repetition. In this system, the waveform is delayed at the optical domain and correlated at the THz domain. Experimental results show clear autocorrelations of 100, 200 and 300 GHz sinusoidal waveforms which indicate the feasibility of the proposed method. [ABSTRACT FROM AUTHOR]

A novel configuration of a multiple‐input multiple‐output (MIMO) circularly polarised (CP) antenna array operating in the C‐band is presented. The array consists of 2 × 2 antipodal tapered slot antenna elements created in the sides of a rectangular as the rectangular grid that supplies a broadband impedance bandwidth and high gain array. To provide broadband MIMO with polarisation diversity, the antenna uses a dual‐port feed network consisting of couplers, a crossover and delay lines which the diversity of polarisation changed by input ports. [ABSTRACT FROM AUTHOR]

On the basis of the technique of time reversal (TR), a new method for low dielectric contrast target detection in clutter by adding dispersive delay lines (DDLs) to each element of the TR mirror (TRM) is proposed. When compared with a conventional TR system, the proposed method improves refocusing to a target by reducing the impact of other scatterers in the environment. The proposed method makes it unnecessary to estimate the position of the target and removes the need for subsequent subtraction as traditionally required. Theoretical and numerical simulated results demonstrate the proposed method. [ABSTRACT FROM AUTHOR]

A compact on‐chip measurement system is proposed for the testing of multiple programmable delay lines (timing digital‐to‐analogue converters (DACs)) through a low‐speed analogue test bus. The system consists of very small delay‐to‐current converters local to each timing DAC, multiplexed to a centrally located programmable‐gain sense amplifier. Silicon test results demonstrate that the system is capable of characterising the delay against the control code relationship of a timing DAC. [ABSTRACT FROM AUTHOR]

To remove glitches occurring in NAND‐based digitally controlled delay lines (DCDLs), a novel glitch‐free architecture is presented. Compared with the previous structures requiring multiple control steps, the proposed DCDL employs a self‐delayed inner loop to remove all the glitches by applying a single‐step control‐code switching, reducing the control complexity remarkably without increasing the minimum delay as well as the resolution. [ABSTRACT FROM AUTHOR]

Phase delay characteristics of the complementary triangular split ring resonator (CTSRR) loaded transmission line with capacitive stubs are presented. The phase responses of a reference microstrip transmission line and a transmission line with capacitive stubs, loaded with the CTSRR on the ground plane, are compared. The practical results show that the CTSRR loaded transmission line provides four times more phase delay when compared with a reference transmission line, and thus the proposed configuration provides a 76% transmission line length reduction. [ABSTRACT FROM AUTHOR]

A reflective metasurface based on the quasi-spiral element is proposed to achieve broadband orbital angular momentum vortex beams for multi-polarisations. The quasi-spiral element can provide linear and smooth phase responses covering about 360° from 10 to 15 GHz with a relative bandwidth about 40% by adjusting the length of four phase delay lines. Additionally, the metasurface can generate vortex beams with optional charges in vertical, horizontal and circular polarisations which are determined by the polarisation of feed antenna. Finally,we have designed and fabricated a 24 x 24 cm² metasurface prototype. The simulated and measured results show that the reflective metasurface can generate broadband vortex beams with orbital angular momentum effectively. As the structure is simple, lightweight and easy to fabricate, the proposed method is applicable to generate broadband vortex beams for multi-polarisations. [ABSTRACT FROM AUTHOR]

The authors demonstrate a photonic link for stable radio frequency (RF) dissemination over fibre based on passive phase compensation with an active-assisted control method. A variable optical delay line is introduced in the transmitting link for active-assisted phase compensation. After active-assisted compensation, the residual jitter is <500 fs. Experimentally, an RF signal at a frequency of 5 GHz is successfully transmitted over a 20-km fibre link, with the stability of 2.49 x 10-14 at 1 s and 9.19 x 10-18 at 104 s. [ABSTRACT FROM AUTHOR]

The authors investigated the problem of overestimation with the Volterra series transfer function (VSTF) and an artificial neural network (ANN), which are used for non-linear equalisers in optical communication systems. The results revealed that the risk of predicting a pseudo-random binary sequence (PRBS) pattern, which causes overestimation of the equaliser performance, occurs not only with an ANN but also with the VSTF. When using PRBS9, PRBS11 and PRBS15, the number of taps of a feedforward tapped delay line, which is required in the VSTF to predict the PRBS pattern, was the same as that with the ANN. When the second-order Volterra kernels were omitted, a larger number of taps was required in the VSTF to observe the overestimation. [ABSTRACT FROM AUTHOR]

A switched delay line phase shifter implemented in a 90 nm SiGe BiCMOS process utilising PIN diodes is presented. The 4‐bit phase shifter utilises four SP4T switches for a simplified architecture. The frequency of operation is from 75 to 100 GHz, and the simulated input referred P1dB is 28.5 dBm. This type of phase shifter is especially suitable for high power transmit linear phased arrays. The chip occupies an area of 2.76 mm2 including the pads. [ABSTRACT FROM AUTHOR]

A precise method of controlling the pulse width using a digital synthesis system is proposed for measurements in the picosecond domain and gigahertz frequency domain. Unlike the traditional pulse synthesise method based on reshapers, the proposed method of synthesising a pulse waveform and adjusting the pulse width is entirely digital. The method realises an ultra‐narrow pulse width by breaking the limit of propagation delay of devices, and the width can be adjusted in fine steps over a wide range (e.g. from a few seconds to hundreds of picoseconds). Programmable delay lines and high‐speed triggers and digital counters within a field‐programmable gate array are used. Experimental results show that the proposed approach generates a pulse that is controllable in 1 ps steps from a minimum width of 100 ps to a maximum width of 1000 s. [ABSTRACT FROM AUTHOR]

The quest continues for microelectronic implementations with higher throughput and reduced power consumption, particularly for digital signal processing, graphic processing unit and CPU portable applications. This Letter focuses on the digital multiplier circuit, which is a key component in determining the power-delay-product for numerous battery powered applications. A proposed radix-4 8 × 8 Booth multiplier is implemented using four stages with a unique optimised stage-1 architecture. Instead of using adder/subtractor in stage-1, it is replaced with a novel binary-to-2’s complement converter and a 2:1 MUX to reduce the delay and power consumption by 7.08 and 49.46%, respectively, compared to the other stages. The proposed design is implemented using CMOS 90 nm technology with 1.2 V supply to demonstrate performance. [ABSTRACT FROM AUTHOR]

A novel group-delay-insensitive linear equaliser (GDILE) is proposed to reduce the eye-skew in four-level pulse amplitude modulation (PAM-4) receivers. With a cross-coupled positive-feedback degeneration network, the proposed GDILE employs additional pole and zero into its transfer function to reduce the group-delay variation with frequency. Simulation results shows a 40 Gbit/s PAM-4 receiver that employs a GDILE that can reduce the eye-skew by 73% compared with the conventional linear equaliser with a modest increase of power consumption. [ABSTRACT FROM AUTHOR]

A low‐cost two‐step delay locked loop (DLL) with a 20–80% input duty cycle is presented. For eliminating harmonic and zero‐trap locking issues along the whole range of digital controlled delay line, a hierarchy phase detector (HPD) is proposed to compare the phase difference between input reference clock and two phase‐isotonic clocks generated by sharing a common delay line. By monitoring of HPD's output, state controller can solve harmonic and zero‐trap locking issues while being naturally immune to the wide range of input duty cycle. With an asymmetric edge combiner, high duty cycle correction accuracy can be achieved. The proposed DLL is implemented in 55 nm CMOS technology with a 0.00574 mm2 chip area. Simulation results show that the operation range of the proposed DLL is 0.3–1.6 GHz without the occurrence of harmonic and zero‐trap locking, and the range of input duty cycle is 20–80%. The power consumption is 0.76 mW at 1.6 GHz. [ABSTRACT FROM AUTHOR]

The existence of the bufferbloat and high-bandwidth non-adaptive flows results in the high queuing delay, which affects the performance of interactive applications, and the inter-flow unfairness, respectively. To solve above-mentioned issues, an efficient active queue management algorithm with Controlling Fairness and Delay (CFD) is proposed. Different from most other schemes, CFD can achieve the low queuing delay and inter-flow fairness simultaneously without the queue isolation. Extensive simulation results also prove the effectiveness and feasibility of CFD. [ABSTRACT FROM AUTHOR]

The use of a delay-locked loop (DLL) for conditioning signals from a surface acoustic wave (SAW) sensor is proposed. The system consists of a reference oscillator and a DLL. The signal generated in the reference oscillator is propagated through a sensitive SAW delay line (SAW-DL). The SAW propagating through this structure has a phase velocity dependent on environmental parameters such as temperature, humidity, mechanical deformation, or analyte concentration. Therefore, the system measures the physical quantity of interest by tracking the delay caused by the sensitive SAW-DL via a DLL. Fully digital DLL is made use of for the delay-tracking, which provides the conversion of the environmental parameter being sensed directly to the digital domain. The system is demonstrated through results from behavioural simulation, using a model of an SAW-DL sensitive to humidity. [ABSTRACT FROM AUTHOR]

A new low-power, fast-locking, all-digital delay-locked loop (DLL) that uses a disposable time-to-digital converter (TDC) is presented for future memory systems beyond double data rate 4. To achieve fast locking and high-frequency operation, the proposed DLL utilises a new hybrid (TDC + binary + sequential) search algorithm that results in a fast locking time of 11 clock cycles without the false lock and harmonic lock problems. By minimising the intrinsic delay of the digital delay line, the proposed DLL achieves an operating frequency range of 1.5-5.0 GHz which is higher than that of the current state-of-the-art all-digital DLLs. The DLL is fabricated in a 65 nm CMOS process and it achieves a peak-to-peak (p-p) output clock jitter of 14 ps (with a p-p input clock jitter of 8 ps) at 5 GHz. The DLL consumes 6.9 mW at 1 V and occupies an active area of 0.025 mm2. [ABSTRACT FROM AUTHOR]

A high-resolution phase frequency detector (PFD) is designed for high-frequency signal detection and low jitter phase locked loop applications. The proposed PFD eliminates the reset path delay and usage of any latches, minimise the dead zone to near zero by generating narrow pulses at each input rising edge. In addition, the designed PFD completely removes unwanted output glitches, accepts inputs with a large difference in frequency, and also has the ability to drive a large capacitive load with minimal impact on performance. The proposed PFD is designed in 90 nm CMOS technology with a 1.2 V power supply. Simulation results indicate that the proposed design can operate over a wide range of frequencies from 10 kHz to 6 GHz and can detect phase differences for inputs as small as 125 fs for all frequencies of operation and for all process corners. The simulated power consumption is 75 μW at 166.6 MHz with an input phase difference of 125 fs. [ABSTRACT FROM AUTHOR]

Analytical expressions for the transfer function and reflection coefficients of the surface acoustic wave (SAW) two-port asymmetrical resonator were obtained using the scattering matrix method. This resonator consists of two different interdigital transducers (IDTs) and reflectors located asymmetrically with respect to the centre of the resonator structure. Equations for the normalised amplitudes for forward and backward travelling SAWs in areas between the IDTs and reflectors have been written and solved. Numerical calculations of the above functions are possible by using the analytical expressions for the admittances and the scattering coefficients of the IDTs and the reflection coefficients of the reflectors. The analytical expressions obtained for the two-port asymmetrical resonator can also be used for the analysis and design of asymmetrical one-port resonators and delay lines. [ABSTRACT FROM AUTHOR]

An integrated optical device that is able to multiplex modulated signals to an optical orthogonal frequency division multiplexing (OFDM) signal directly in the optical domain is demonstrated. The device operates based on optical inverse fast Fourier transform (IFFT). It is composed of directional couplers, delay lines and a combiner, which was fabricated with silica waveguide technology. The operation was experimentally confirmed by generating 40 and 80 Gbit/s optical OFDM signals. [ABSTRACT FROM AUTHOR]

On the basis of the technique of time reversal (TR), a new method for low dielectric contrast target detection in clutter by adding dispersive delay lines (DDLs) to each element of the TR mirror (TRM) is proposed. When compared with a conventional TR system, the proposed method improves refocusing to a target by reducing the impact of other scatterers in the environment. The proposed method makes it unnecessary to estimate the position of the target and removes the need for subsequent subtraction as traditionally required. Theoretical and numerical simulated results demonstrate the proposed method. [ABSTRACT FROM AUTHOR]

A new configuration of a circularly polarised square slot antenna (CPSSA) array operating in C-band is presented. The array consists of 2 × 2 CPSSA elements and is fed by a novel feeding network consisting of the circuit stripline couplers and delay lines. The proposed feeding technique is applied to the 2 × 2 antenna array to increase the axial ratio (AR) bandwidth. The measured impedance bandwidth for a voltage standing wave ratio (VSWR) <2 is around 78.5% (3.4–7.8 GHz), the 3 dB AR bandwidth is about 35.7% (4.6–6.6 GHz) and the antenna has an average 14.2 dBic gain over the 3 dB AR bandwidth. The measured results corroborate well with the simulated results. [ABSTRACT FROM AUTHOR]

To remove glitches occurring in NAND-based digitally controlled delay lines (DCDLs), a novel glitch-free architecture is presented. Compared with the previous structures requiring multiple control steps, the proposed DCDL employs a self-delayed inner loop to remove all the glitches by applying a single-step control-code switching, reducing the control complexity remarkably without increasing the minimum delay as well as the resolution. [ABSTRACT FROM AUTHOR]

A time-to-digital converter (TDC) for a low-power, wide-range all digital phase-locked loop (ADPLL) is presented. The proposed TDC uses an enabling signal with variable duration to achieve low power and wide range. For verification purpose, the ADPLL is fabricated in a 0.11 μm CMOS technology. The ADPLL dissipates 6.02mW at an output frequency of 1.68GHz and its output frequency is measured as 0.24-1.68 GHz from a 1.2 V supply. [ABSTRACT FROM AUTHOR]