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A synergetic-equalisation coding scheme for pulse-amplitude modulation 4-level (PAM4) is proposed, based on which a 216 Gb/s 9-bit 8-wire 4-level (9B8W4L) transceiver is designed. According to the scheme, eight channels are grouped into four pairs based on the states for encoding. The two channels in pair transmit the same symbol in this unit interval (UI), and transmit different symbols in different pairs in the next UI. When decoding, the symbols in different channels are subtracted from and added with the others, following the grouping in the prior UI. From this, the first post-cursor inter-symbol interference is eliminated. Based on the proposed coding scheme, the PAM4 transceiver transmits 9-bit data by eight channels, giving a channel utilisation of 112.5%. The improvement of channel utilisation reduces the Nyquist frequency for the same data rate, which is of great significance for reducing channel loss and power consumption. The 216 Gb/s 9B8W4L transceiver with 1-tap feed-forward equaliser achieves a bit error rate

The authors investigated the problem of overestimation with the Volterra series transfer function (VSTF) and an artificial neural network (ANN), which are used for non-linear equalisers in optical communication systems. The results revealed that the risk of predicting a pseudo-random binary sequence (PRBS) pattern, which causes overestimation of the equaliser performance, occurs not only with an ANN but also with the VSTF. When using PRBS9, PRBS11 and PRBS15, the number of taps of a feedforward tapped delay line, which is required in the VSTF to predict the PRBS pattern, was the same as that with the ANN. When the second-order Volterra kernels were omitted, a larger number of taps was required in the VSTF to observe the overestimation.

An adaptive continuous-time linear equaliser using the optimised spectrum balancing (SB) method is proposed. The SB method is extended with a frequency detector to promote compensation ability of an equaliser and completes the optimal equalisation decision for multi-data rates. The active inductor peaking technology is adopted to increase the bandwidth of an equaliser, save chip area and power consumption. Based on Huaili Microelectronics Corporation (HLMC) 40 nm CMOS process to achieve the overall design, the power consumption and chip area are 32.11 mW at 20 Gbit/s and 0.14 mm2, respectively. And it can offer a compensation range from 6 to 18 dB for 5–20 Gbit/s of receiving data.

A two-switch equaliser for series-connected battery stack using zeta type converter and symmetrical capacitor-diode circuit is proposed. The proposed equaliser consists of a zeta type front-end dc-dc converter and symmetrical capacitor-diode circuit, uses only two active switches and two magnetic components, thus it benefits from small circuit volume and flexible for extension. Meanwhile, it can work under open loop, which makes its control simple. Furthermore, high efficiency is achieved by zero voltage switching of all switches. Finally, experimental results of a prototype of the proposed equaliser are presented to verify the analysis results.

Retrieving original user data from holographic data storage systems is mainly affected by two-dimensional (2D) intersymbol interference; the minimisation of this interference not only improves the system performance, but it also increases the storage density for page-oriented storage systems. An iterative detection that is supported by the readback signal is proposed. The decoded symbols are passed through a 2D partial response target before they are combined with the output of the equaliser, leading to the generation of a refined information source that improves the channel-detection performance. The simulation results show that the proposed structure provides a gain of ∼1–2 dB; furthermore, the combinative quality of the proposed model and a page-based search scheme were analysed as well.

Analogue-to-digital-converter-based (ADC-based) backplane receivers have been widely studied in recent years as ever-increasing data rate calls for strong equalisation. However, despite their ability to support various types of digital equalisation techniques, most receivers rely on linear finite-impulse-response-filter-based (FIR-filter-based) equalisers that are susceptible to quantisation error of the front-end ADC. This Letter proposes a non-linear maximum-likelihood-estimation-based (MLE-based) equaliser that utilises channel output distribution and probability theory to make bit decisions. The proposed non-linear algorithm achieves robust performance against quantisation noise of the front-end ADC. Moreover, a feed-forward equaliser can be implemented without involving multi-bit multipliers and adders that cause serious hardware complexity overhead. Simulation results suggest that the proposed MLE-based equaliser can improve bit error rate (BER) by 1010 times with a 5-bit front-end ADC and save front-end ADC bit resolution by more than 0.8 bits with BER of 10−15, when compared with the conventional FIR-filter-based equaliser.

The stochastic gradient algorithm presented employs the time-varying neuron's slope to optimise performing of the all-pole filter-whitener maximising the joint Shannon's entropy. By using the time adaptive slope, which matches the unknown probability density function of an input process, a neuron slope selection issue of the original algorithm is facilitated and its tracking of non-stationary statistics is improved. The performing of algorithm is verified using the whitener as a front-end amplitude equaliser of the blind equaliser.

A 40 Gbps 4-tap 4-level pulse amplitude modulation closed-loop decision feedback equaliser (DFE) is proposed. The DFE adopts a novel high-speed comparator to resolve the critical timing constraints of the first tap. The comparator decreases the slicing delay by shortening the gap between initial and target voltages. Compared with the existing closed-loop DFE designs, the proposed scheme relieves timing constraints without complex clock distribution circuits and extra area. Simulations based on the RF-MOS model verify that the delay of the comparator is improved by 32.8% and the output swing is increased by more than 2.8 times. The proposed DFE which can compensate −9.5 dB channel loss is designed in 55 nm CMOS technology. The power consumption is 67 mW from a 1.2 V supply and the circuit occupies an active area of 0.021 mm2, achieving 1.68 pJ/bit energy efficiency.

A 10 Gbit/s serial link receiver with an offset-calibrated continuous-time linear equaliser, an adaptive one-tap half-rate speculative decision feedback equaliser (DFE) and a phase-interpolator-based clock and data recovery is presented. Adaption of the DFE is achieved by using a novel mixed-signal implementation of the sign-sign least mean square algorithm to save the cost of hardware and power. Fabricated in 65 nm CMOS technology, the receiver can totally compensate 24.85 dB channel loss at a bit error rate of 10−12. The active chip area is 0.08 mm2 and the total power consumption is 57 mW from a 1.2 V supply.

A fractional-norm constrained blind adaptive algorithm is presented for sparse channel equalisation. In essence, the algorithm improves on the minimisation of the constant modulus criteria by adding a sparsity-inducing lp-norm penalty (0 < p ≤ 1). The simulation results demonstrate that the proposed equaliser exploits the inherent channel sparsity effectively and exhibits faster convergence compared with its counterparts.

To reduce pattern-dependent jitter in four-level pulse-amplitude modulation (PAM-4) signalling, a transition-aware feed-forward equaliser (TFFE) is proposed. By allowing the transition time to vary according to the transition types of the PAM-4 symbols, switching jitter in TFFE-based PAM-4 transmitters can be greatly suppressed, down to the non-return-to-zero (NRZ) level. Simulation results confirm that a PAM-4 transmitter that employs a TFFE can reduce the jitter level by 0.18 unit interval peak-to-peak, and this proposed equaliser can achieve nearly identical eye height as the conventional PAM-4 feed-forward equalisers design without introducing any signal-to-noise ratio penalty.

An analogue equaliser with a novel digitally tuned variable degeneration resistance is realised in a 65 nm CMOS technology. Implemented with three parallel resistance branches and one serial resistance branch to well fit the optimal conductance curve, the proposed variable degeneration resistance is exploited to achieve a wide boost range while significantly improving the linearity of the tuned boost factors compared with the equaliser with a traditional degeneration resistance structure.

The design of a 4× blind analogue-to-digital converter (ADC)-based receiver implemented in 65 nm CMOS technology is presented. The ADC, which has three levels with two adjustable thresholds, effectively implements a speculative decision-feedback equaliser. By reducing the ADC resolution and by simplifying the digital clock and data recovery design, the power consumption is reduced by a factor of 2 compared with previous works. Measurement results confirm a bit error rate of

Optimal power allocation (PA) and sub-carrier pairing (SP) strategies for a dual-hop amplify-and-forward single-carrier frequency division multiple access network are derived. Frequency domain equalisers based on minimum mean square error (MMSE) and zero forcing (ZF) criteria are considered. For each equaliser, the problem of joint PA and SP is solved to maximise the system capacity subject to the total network power constraint. The optimality of ordered SP (OSP) and reverse OSP scenarios for MMSE and ZF equalisers, respectively, is proved.

A simple method for dynamically adjusting the tap-length adaptation step-size of a variable tap-length linear equaliser based on the fractional tap-length algorithm is presented. Simulations show that the technique provides a fast convergence of tap-length and small steady-state tap-length fluctuation.

An adaptive frequency-domain equaliser for the single carrier frequency division multiple access (SC-FDMA) system using the particle swarm optimisation (PSO) technique is proposed. Unlike the stochastic gradient and recursive least squares algorithms, the PSO is known to have fast convergence which does not depend on the underlying structure. The cost function used in a PSO is formulated based on the respective structure of the equaliser, whether it is a linear equaliser or a decision feedback equaliser. The robustness of the proposed PSO algorithm is demonstrated on a high Doppler scenario. Furthermore, it is shown that the performance improves more when using re-randomisation. Finally, it is shown that the PSO-based frequency-domain equaliser is more computationally efficient than its time-domain counterpart.

The low complexity receiver structure based on discrete cosine transform for a downlink multicarrier code division multiple access (DCT-MC-CDMA) system is proposed. It employs an interference cancellation scheme with a linear equaliser to suppress the multiple access interference and interference caused by the multipath fading channel The performance of the proposed receivers is analysed and compared to the conventional downlink DFT-MC-CDMA system. Simulation results show a large performance improvement when using such an interference cancellation scheme relative to the DCT equalisation receiver, and interference cancellation for the downlink DFT-MC-CDMA system.

A novel iterative equaliser, the 2-dimensional iterative soft decision interference cancellation (ISDIC) (2D ISDIC) equaliser, is introduced. The 2D ISDIC is the first equaliser that bridges the gap between the low-complexity ISDIC equaliser which has poor performance, and the high-complexity inverse-channel equalising methods, such as the LMMSE and the MMSE ISDIC equalisers, which have better performances. The 2D ISDIC will be incorporated into the turbo equalisation scheme, resulting in an enhanced turbo equaliser, that performs better than the conventional, state of the art, linear turbo equaliser, with lower complexity and lower amount of iterations.

A design technique for performing low-power decision-feedback equalisation for multi-Gbit/s serial links is presented. The technique systematically reduces the capacitive loading on the timing-critical node within the feedback loop of the equaliser. Based on the proposed technique, an architecture capable of both equalisation and digitisation of the received data is presented. Power efficiency of the proposed architecture is analysed and is compared with that of conventional analogue and loop-unrolled decision-feedback equalisers. The technique is validated through a proof-of-concept chip fabricated in 65 nm CMOS.

Proposed is a zero-inserting precoder and a two-stage linear equaliser, to shorten the guard interval in block-based single-carrier modulation. The first-stage equaliser consists of a linear single-tapper-subcarrier frequency-domain equaliser. The second-stage equaliser maximises the SINR, in the time-domain, based on the interference-plus-noise estimated from the zero-padded sub-intervals of the single-carrier modulation. This proposed scheme is applicable even without cyclic prefixing.

A quality of transmission (QoT)-aware adaptive adjustment scheme of optical path transmission performance under software control is proposed. First, a mathematical model of optical path transmission performance adjustment is established. Based on it, a new device link quality equaliser (LQE) is built. Second, using a centralised controller, the LQE introduces devices with different compensation abilities into the optical path. Therefore, it becomes an all-optical mode node or an optical–electrical–optical (O/E/O) mode node adaptively. Then an adaptive and elastic adjustment can be conducted on the transmission performance of the optical path. Finally, an experiment is presented to show the feasibility and effectiveness of the proposed scheme.

An open-stub compensation technique is proposed for passive equalisers used in high-speed digital communication systems. By simply lumping an open stub to the conventional RL-type passive equaliser, the frequency-dependent channel loss from the long transmission path can be compensated, the frequency response of the channel becomes more flat and the bandwidth is wider. On comparing the proposed passive equaliser with typical RL passive equalisers, the simulation results show that the proposed technique can achieve an improvement by 1 GHz in the flat region of S 21 on a 60 cm-long differential pair. Thus, the proposed technique successfully demonstrates an improvement in electrical performance of about 57.4% in the time domain.

Traditionally, frequency-domain equalisers have been used to equalise the single-carrier block transmission (SCBT) signals. However, to support the frequency-domain equaliser, two fast Fourier transform modules are required, which will increase the circuit complexity and chip area. A low-complexity time-domain linear equaliser for SCBT is proposed, which is less complicated than conventional frequency-domain equalisers, at the expense of an acceptable degradation in performance. For instance, for 60 GHz conference room non-line-of-sight channels, the complexity can be reduced by half at the expense of a 1.5 dB performance loss.

The effectiveness of a variable group-delay dispersion equaliser in compensating for the dispersions of various lengths of fibre is explained. The variable dispersion equaliser has a lattice-form programmable optical filter configuration and its dispersion can be varied from -681 to 786 ps/nm. The dispersion of three different fibres has been compensated for with a single equaliser.

The authors consider the design of quadrature mirror filter (QMF) banks using digital allpass filters. The QMF banks consisting of an allpass filter and a pure delay section have an approximately linear phase response, and the phase distortion can be minimised by using another additional allpass filter as an equaliser.

A complex fuzzy adaptive filter based on the RLS algorithm is presented. The inputs and outputs of the fuzzy filter are both complex valued. The fuzzy filter, used as an adaptive equaliser, is applied to 4-QAM digital communication with nonlinear complex channel characteristics. The bit error rates of the fuzzy equalisers are close to those of the optimal equaliser.

The authors report an integrated-optic dispersion equaliser with an amplitude flattening circuit on a planar lightwave circuit. The equaliser consists of six asymmetrical Mach-Zehnder interferometers cascaded in series. The operational frequency range of the equaliser is successfully extended from 12.6 to 21.2 GHz by amplitude flattening without deteriorating the delay characteristics.

A clock extraction technique based on using the equaliser tap settings to provide feedback of the timing position is proposed for modems. It is shown how the necessary fine adjustment of the clock phase can be achieved with discretely varied timing clocks. The clock extractor is particularly appropriate for distorted channels, requires little processing and is suitable for fast-train operation.

128 channel, 622 Mbit/s FSK-DD transmission is demonstrated using dispersion-shifted fibres, total fibre length of 480 km, with 13 inline 0.98 µm pumped erbium-doped fibre amplifiers (EDFAs) and a tunable gain equaliser. The gain imbalance and noise figure of the 0.98 µm pumped EDFAs are small compared to those of 1.48 µm pumped EDFAs, and the residual gain imbalance can be compensated for by just one waveguide-type tunable gain equaliser. As a result, all channels were successfully transmitted with power penalties of less than 1 dB.

As a new approach to the equalisation of nonlinear channels, a fuzzy adaptive decision feedback equaliser based on a fuzzy adaptive filter is proposed. With perfect knowledge of the channel, the proposed method not only improves equalisation performance but also reduces the computational complexity compared with the conventional fuzzy adaptive filter.

Prior work has focused on the negative aspects of time-dispersive channels and associated intersymbol interference. The authors show that the inherent diversity introduced by such dispersion is advantageous in reducing the performance-limiting effects of flat fading. This is demonstrated for an indoor QPSK radio link employing a decision-feedback equaliser. >

A new prefilter structure is presented. The frequency response of the prefilter structure is derived from the combination of two cosine functions. By cascading these prefilters with an appropriate equaliser, low complexity filters with high stop-band attenuation can be achieved. The proposed prefilter leads to a significant saving in the number of arithmetic operations in the prefilter-equaliser cascade structure.

Performance results are given for the combined use of a decision feedback equaliser with antenna diversity in time dispersive Rayleigh fading channels such as those typically encountered in narrowband digital cellular mobile systems. The results show that the use of dual antenna diversity provides significant gains over nondiversity receivers with decision feedback equalisers, and that this performance is robust in the presence of uncompensated paths and correlations between the diversity ports

Proposed is a symbol-based decision-directed algorithm for blind equalisation of quadrature amplitude modulation (QAM) signals using a decision feedback scheme. Independently of QAM order, it presents: (i) an error equal to zero when the equaliser output coincides with the transmitted signal; (ii) simultaneous recovery of the modulus and phase of the signal; (iii) a misadjustment close to that of the normalised least-mean squares algorithm; (iv) fast convergence; and (v) the avoidance of degenerative solutions. Additionally, its stability is ensured when the step-size is properly chosen.

Demonstrated is a record serial transmission rate of 42.8 Gbit/s by sending four-level pulse amplitude modulated (PAM-4) data over a low-loss Megtron 6 electrical backplane. The data is processed and equalised using early late gate timing recovery and a finite-impulse-response-based least-mean-squares equaliser. Bit error rate performance is reported over several different links.

A high-speed transmission over step-index plastic optical fibre (SI-POF) using a resonant cavity light emitting diode (RCLED) is described. The integrated optical receiver is realised in 0.6 µm BiCMOS technology with an integrated large-area Si photodiode. The design consists of a TIA, equaliser and post-amplifier stage followed by a 50 Ω output driver. The integrated equaliser can be adapted via an external control voltage to different SI-POF lengths and RCLED limited bandwidths. A data rate of 250 Mbit/s can be transmitted over a 50 m-long SI-POF with a sensitivity of −22dBm at BER of 10−9 and over a 100 m-long SI-POF with a sensitivity of −24 dBm at a BER of 10−6.

A complete 30 Gbit/s VCSEL link is reported. The driver and receiver amplifiers were fabricated in a 0.13 m SiGe BiCMOS process and the 850 nm VCSELs and photodetectors are commercial 10 Gbit/s-class components. Transmitter pre-emphasis applied through the feed-forward equaliser circuit enables the full link to operate at 30 Gbit/s at a bit error ratio less than 10 -12 with a 9 dB link budget.

Rayleigh backscattering (RBS) causes significant power penalty in a centrally light-seeded wavelength division multiplexed passive optical network (WDM-PON). In this reported work, the RBS noise in a WDM-PON based on a reflective semiconductor optical amplifier (RSOA) is successfully mitigated by means of noise predictive equalisation. Conventional equalisers are implemented at the receiver with an additional noise canceller that can estimate and reduce the reflection noise. It is experimentally demonstrated that the proposed equaliser enhances the reflection tolerance significantly at data rates of 2.5 and 10 Gbit/s to −8.5 and −16.5 dB, respectively.

A novel dynamic linear equaliser circuit is proposed for high-speed transceiver applications. The evaluation phase of a strong-arm latch is exploited to provide equalisation while sampling the input data. The circuit does not require any special biasing and only consumes power during transitions, which makes it superior compared to traditional continuous-time linear equalisers followed by samplers in terms of power efficiency and process scalability.

Proposed is an effective approach to suppress noise interference in wireless communications, the expanded time-frequency (ETF-) OFDM system with joint time-frequency spreading. However, in this system, the orthogonality of the spreading code can be destroyed by multipath fading. Developed is a scheme that employs a zero-forcing equaliser at the receiver and assigns spreading codes at the transmitter for this system. Simulation results show that the ETF-OFDM system with the proposed scheme can take advantage of multipath fading to boost performance.

Artificial neural network techniques have become very common as equalisation solutions in several types of communication channels. These neural networks are presented in many topologies. The suitable choice of a topology for equalisation purpose depends on different criteria such as: convergence rate, bit error rate, computational complexity, among many others. Reported is an investigation into the behaviour of a structure similar to a decision feedback equaliser employed to equalise time-varying channels. The structure, a single recurrent perceptron, is based on a simplified recurrent neural network. The Gauss-Newton algorithm has been used to estimate the synaptic weights of the perceptron during the training and testing phases. Despite the simplicity of implementation and low computational cost, it has been shown that the proposed topology presents some good comparative performances compared with more complex structures based on recurrent neural networks and multilayer perceptrons using Kalman filters.

Low-complexity blind turbo receivers composed of a soft-feedback equaliser (SFE) and fast least-squares (FLS) channel estimators are proposed. To reduce the complexity of the SFE computation, a function approximation is proposed instead of numerical algorithms in a specific step of the equaliser's computation. Concerning FLS channel estimators, a specific filter parameters initialisation procedure is proposed in each turbo iteration to avoid possible numerical instabilities. Estimation of noise variance is also considered. The proposed scheme can perform as the turbo equaliser with perfect channel knowledge from a certain signal-to-noise ratio.

The mitigation of intra-channel nonlinearities in 10 Gbaud coherent NRZ-QPSK systems via a nonlinear electrical equaliser based on Volterra theory is experimentally demonstrated. Without the requirement of prior knowledge of the fibre link, the equaliser significantly improves the system performance compared to digital dispersion compensation only.

The use of a variable detection delay is proposed to improve the bit error rate and error propagation characteristics of a dual decision-feedback equaliser.

An oversampled subband equaliser is designed for chromatic dispersion of singlemode optical fibre. The signal of each subband is equalised individually and delayed to align with other subbands. From simulation, the overall number of equaliser taps is approximately reduced by the upsampling ratio.

An area- and power-efficient analogue adaptive equaliser (AEQ) is realised in a 0.13 m CMOS technology. The negative capacitance circuits are exploited at the equalisation filter to achieve wider bandwidth and larger high-frequency boosting, instead of using passive inductors that lead to a large chip area. Measured results demonstrate the data rate of 10 Gbit/s for 20 and 34 inch FR4 traces as channels, while dissipating only 6 mW from a single 1.2 V supply. The chip core occupies an extremely small area of 50 times 130 m 2 . To the best of the authors' knowledge, this chip achieves the lowest power consumption and the smallest chip area among the recently reported AEQs.

A low-complexity detection scheme consisting of a sphere decoder and a parallel interference cancellation (PIC) equaliser is proposed for OFDM systems in doubly-selective fading channels. Theoretical analysis and simulation results show that this detection scheme substantially improves the symbol error rate performance of OFDM systems compared with the traditional PIC equaliser while requiring lower complexity at moderate and high signal-to-noise ratios.

An improved adaptive blind decision feedback equaliser (DFE) scheme in the presence of rapidly time-varying channels is proposed by utilising a soft decision feedback sample generator for reduction of error propagation and, at the same time, for enhancement of (re)initialisation and tracking ability of the DFE.

A modified constant modulus (CM) algorithm based blind multiuser equaliser with a decision directed (DD) scheme is developed that does not require any mutual decorrelation and is suitable for downlink direct sequence code division multiple access systems. The performance of the proposed time domain adaptive equaliser is evaluated with respect to usual parameters and is found to perform better than the concurrent CM algorithm and DD scheme.