Dynamic linear equaliser circuit

Authors :: Taner Sumesaglam
Source :: Electronics Letters. 47:642
Publication Year :: 2011
Publisher :: Institution of Engineering and Technology (IET), 2011.
Abstract: A novel dynamic linear equaliser circuit is proposed for high-speed transceiver applications. The evaluation phase of a strong-arm latch is exploited to provide equalisation while sampling the input data. The circuit does not require any special biasing and only consumes power during transitions, which makes it superior compared to traditional continuous-time linear equalisers followed by samplers in terms of power efficiency and process scalability.