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Silicon-Germanium (SiGe) is a material that possesses a multitude of applications ranging from transistors to eletro-optical modulators and quantum dots. The diverse properties of SiGe also make it attractive to implementations involving superconducting quantum computing. Here we demonstrate the fabrication of transmon quantum bits on SiGe layers and investigate the microwave loss properties of SiGe at cryogenic temperatures and single photon microwave powers. We find relaxation times of up to 100 $\mu$s, corresponding to a quality factor Q above 4 M for large pad transmons. The high Q values obtained indicate that the SiGe/Si heterostructure is compatible with state of the art performance of superconducting quantum circuits., Comment: 5 pages, 3 figures

The effect of hot carrier injection on the FET's junction properties has been investigated for CMOS NFET devices. Junction profiles and carrier concentration of stressed and unstressed devices are measured and compared by dual lens electron holography and scanning capacitance microscopy, respectively. The measurements reveal that the width of the junction on the drain side of the device that undergoes hot carrier stressing decreases, indicating a reduction in active carrier concentration. These results are consistent with the hypothesis of phosphorous dopant passivation by the hot carrier induced release of hydrogen into the drain side extension region.

III–V nanoscale devices were monolithically integrated on silicon-on-insulator (SOI) substrates by template-assisted selective epitaxy (TASE) using metal organic chemical vapor deposition. Single crystal III–V (InAs, InGaAs, GaAs) nanostructures, such as nanowires, nanostructures containing constrictions, and cross junctions, as well as 3D stacked nanowires were directly obtained by epitaxial filling of lithographically defined oxide templates. The benefit of TASE is exemplified by the straightforward fabrication of nanoscale Hall structures as well as multiple gate field effect transistors (MuG-FETs) grown co-planar to the SOI layer. Hall measurements on InAs nanowire cross junctions revealed an electron mobility of 5400 cm2/V s, while the alongside fabricated InAs MuG-FETs with ten 55 nm wide, 23 nm thick, and 390 nm long channels exhibit an on current of 660 μA/μm and a peak transconductance of 1.0 mS/μm at VDS = 0.5 V. These results demonstrate TASE as a promising fabrication approach for heterogeneou...

Atomic layer deposition (ALD) of epitaxial c-axis oriented BaTiO3 (BTO) on Si(001) using a thin (1.6 nm) buffer layer of SrTiO3 (STO) grown by molecular beam epitaxy is reported. The ALD growth of crystalline BTO films at 225 °C used barium bis(triisopropylcyclopentadienyl), titanium tetraisopropoxide, and water as co-reactants. X-ray diffraction (XRD) reveals a high degree of crystallinity and c-axis orientation of as-deposited BTO films. Crystallinity is improved after vacuum annealing at 600 °C. Two-dimensional XRD confirms the tetragonal structure and orientation of 7–20-nm thick films. The effect of the annealing process on the BTO structure is discussed. A clean STO/Si interface is found using in-situ X-ray photoelectron spectroscopy and confirmed by cross-sectional scanning transmission electron microscopy. The capacitance-voltage characteristics of 7–20 nm-thick BTO films are examined and show an effective dielectric constant of ∼660 for the heterostructure.

Thin carbon films were deposited by ion beam sputtering at temperatures of 77–1073 K. Using Rutherford backscattering spectrometry and electron energy loss spectroscopy, the trends in film density and bonding were examined as a function of deposition conditions. It has been found that film density and sp3 bonding character unexpectedly increased with increased substrate thermal conductivity and decreasing substrate temperature, reaching values of 2.9 g/cc and 50%, respectively.

Detailed analysis of a buried layer of GaAs in 〈100〉 Si was carried out using electron energy loss spectroscopy, Rutherford backscattering spectroscopy, and ion channeling. The layer was formed by 200 keV dual ion implantation of Ga plus As ions, followed by furnace annealing at 600 and 950 °C. It consists of GaAs particles which are surrounded by fully recrystallized silicon. Beneath it is a dislocation network, made up of a mixture of edge and screw dislocations.

Dual lens dark field electron holography and Moire fringe mapping from dark field scanning transmission electron microscopy are used to map strain distributions at high spatial resolution in Si devices processed with stress memorization techniques (SMT). It provides experimental evidence that strain in the Si channel is generated by dislocations resulting from SMT. The highest value of strain, up to 1.1% (1.9 GPa in stress) occurs at the Si surface along the channel direction: ⟨110⟩. An increase of ∼0.2% strain in the channel is observed after removing the poly-Si gate through the replacement high-k metal gate process.

Yttrium lanthanum silicate was formed in direct contact with silicon after a rapid thermal annealing at 1000 °C in metal-oxide-semiconductor capacitors leading to an equivalent oxide thickness (EOT) of 7.7 A. This represents one of the lowest EOT value reported for a gate-first process with non Hf-based dielectric. The silicate is formed by interdiffusion of La2O3 and YOx layers and interfacial SiO2 consumption. Yttrium incorporation reduces the leakage current density as well as the large negative flatband voltage (Vfb) shift that is associated with lanthanide-based dielectrics. The Vfb value can be appropriately tuned for n-type field-effect transistor operation by changing the silicate composition.

LaxLu1−xO3 thin films were deposited on 300 mm silicon wafers by physical vapor deposition and fabricated into field-effect transistors using a gate-first process flow. The films were characterized using transmission electron microscopy, Rutherford backscattering spectrometry, and synchrotron x-ray diffraction. The results show the films remain amorphous even at temperatures of 1000 °C. The dielectric properties of LaxLu1−xO3 (0.125≤x≤0.875) thin films were evaluated as a function of film composition. The amorphous LaxLu1−xO3 thin films have a dielectric constant (K) of 23 across the composition range. The inversion thickness (Tinv) of the LaxLu1−xO3 thin films was scaled to

We discuss the structural and electrical properties of scaled 2 nm HfO2/SrO gate stacks. Thin SrO layers are deposited by molecular beam epitaxy onto (001) p-Si substrates as alternative passivating interfacial layers (ILs) to SiO2. X-ray photoelectron spectroscopy and transmission electron microscopy show that, despite some HfO2–SrO intermixing, the SrO IL acts as a barrier against HfxSiy and SiO2 formation during high-κ deposition. Electrical measurements on metal-oxide-semiconductor capacitors with TiN metal gates integrated in a low-temperature process flow reveal an equivalent oxide thickness of 5 A with competitive leakage current and hysteresis and a negative flat band voltage shift, suitable for n-channel transistors.

We demonstrate metal-gate-induced interfacial layer (IL) scaling using a HfO2 dielectric and clarify the kinetics underlying this process. The intrinsic IL scaling effect on electron mobility is separated from La and Al-induced dipole effects. We find that the mobility degradation for La-containing high-κ dielectrics is not due to the La-induced dipole but due to the intrinsic IL scaling effect, whereas the Al-induced dipole brings about additional mobility degradation. This unique nature of the La-induced dipole enables aggressive equivalent oxide thickness scaling down to 0.42 nm without extrinsic mobility degradation when combined with IL scaling.

We present evidence for the instability in the crystalline (metallic) state of binary Te-free phase-change Ge–Sb thin films considered for integration into nonvolatile nanosized memory cells. We find that while the amorphous (semiconducting) phase of eutectic Sb–15at.% Ge is very robust until Sb crystallization at 240°C, at about 350°C, germanium rapidly precipitates out. Ge precipitation, visualized directly with transmission electron microscopy, is exothermic and is found to affect the films’ reflectivity, resistance, and stress. It converts melting into a two-step process, which may seriously impact the switching reliability of a device.

The authors present direct evidence for Te segregation to the grain boundaries in chalcogenide Ge2Sb2Te5 films by using transmission electron microscopy scans with a 0.5nm diameter focused probe. This finding is consistent with the observed impeded grain growth and with the post-transition relief of a “spikelike” stress, fully to the pretransition level. Te motion shows up in void formation below 200°C, a pileup of Te at the surface and its loss at higher (above 400°C) temperatures. Tuning the driving force for this segregation may be key for the optimal phase-change material design.