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An analog memcapacitor has been created by a ferroelectric capacitor. Since the memcapacitor is a capacitor, the power consumption is not dissipated at all in principle. The device structure is that a ferroelectric layer is sandwiched between the bottom electrode and the top electrode. The analog memcapacitor characteristic is realized, namely, varying Vmax is applied, and the capacitance is strongly dependent on it. The working principle can be explained by the operating point analysis for the intrinsic property of the ferroelectric layer. If the memcapacitors are implemented in neuromorphic systems, it is expected that the power consumption will be remarkably reduced. It has been simulated that the spiking neuromorphic system dissipates only 6.24 nJ/Inference for MNIST inference with acceptable accuracy, which is much lower than other systems.

Artificial intelligence is used for various applications and is promising as an indispensable infrastructure in future societies. Neural networks are representative technologies that imitate human brains and exhibit various advantages. However, the size is bulky, the power is huge, and some advantages are not demonstrated because they are executed on Neumann-type computers. Neuromorphic systems are biomimetic systems from the hardware level to implement neuron and synapse elements, and the size is compact, the power is low, and the operation is robust. However, because the conventional ones are not composed of fully optimized hardware, the power is not yet minimal, and extra control circuits must be used. In this article, we developed a neuromorphic system using memcapacitors and autonomous local learning. By using memcapacitors, the power can be minimal, and by using autonomous local learning, the control circuits to handle the synapse elements can be deleted. First, the memcapacitors are completed in a cross-bar array, where the ferroelectric layers are sandwiched between the horizontal and perpendicular electrodes. The polarization and capacitance exhibit hysteresis due to the dielectric polarization. Next, autonomous local learning is introduced as follows. During the training phase, associative patterns to be memorized are directly sent, relatively high voltages are applied, and dielectric polarizations are induced. During the operation phase, relatively low voltages are applied, and input signals are weighted with the capacitances of the memcapacitors, summed, and transferred as the output signals. Finally, the experimental system is set up, and the experimental results are acquired. The memorized patterns during the training phase, distorted patterns as the input signals during the operation phase, and retrieved patterns as the output signals in the operation phase are shown. Researchers found that the retrieved patterns are completely the same as the memorized patterns. This means that the neuromorphic system works as an associative memory.

Ferroelectric-gate field-effect transistors (FeFETs) with a bottom-gate geometry consisting of a ferroelectric HfO2gate and an oxide channel have been intensively studied in recent years. However, there has been no detailed investigation into the impact of atmospheric exposure on device performance, even though the channel is often exposed to ambient air for process simplification, especially at the research stage. In this study, the ambient stability of an indium tin oxide channel FeFET with a ferroelectric Ce-HfO2bottom gate was investigated. We found that ambient degradation of the gate controllability was caused by an increase in physisorbed water in the device owing to the intrusion of moisture. Mobile ions, such as H+, which can easily move through a network of hydrogen bonds formed by adjacent physisorbed water, may compensate for ferroelectric polarization. Finally, we demonstrated that the observed degradation can be managed effectively without compromising the original device characteristics using Al2O3passivation gently formed via plasma-free deposition.

Electron energy loss spectroscopy—spectrum imaging measurements using a scanning transmission electron microscope are carried out to clarify the details of microstructure at the interface of the CeOx-capped Y-HZO film prepared by the chemical solution deposition (CSD) method. We confirmed that by the present CSD the independent capped layer of CeOxsuccessively deposited on Y-HZO. The crystal structure of CeOxfilm is mainly the cubic CeO2structure with Ce4+. Chemical state maps are also successfully obtained by the multivariate analysis. We found that Ce3+and Ce4+coexist in the interface layer with cubic CeO2crystal structure containing O vacancy. The results of the quantitative elemental distribution maps of energy dispersive X-ray spectroscopy also supported that O vacancies exist at the interface.

Multivalent oxide, CeOxhas been formed at the top or bottom of the Hf-Zr-O (HZO) layer by chemical solution deposition (CSD) to obtain the ferroelectric properties of the HZO layer. It is shown that the insertion of a thin CeOxlayer significantly enhances the ferroelectric properties of the Y-doped HZO layer. It is found by transmission electron microscope observation that a CeOx(12 nm)/Y-HZO(33 nm) layered structure can be clearly fabricated by the CSD process in spite of high temperature crystallization anneal at 800 °C.

We demonstrate a three-terminal variable-area capacitor integrated with a ferroelectric-gate field-effect transistor (FeFET) and a ferroelectric capacitor. A FeFET using an indium tin oxide (ITO) channel and a ferroelectric Hf0.86Ce0.14O2gate insulator was fabricated by chemical solution deposition. The fabricated FeFET exhibited a high on-current of ∼0.18 mA μm−1and a large on-/off-current ratio of 106. The large charge controllability of the FeFET allows the conductive ITO channel to act as an electrode switch that connects and disconnects two capacitors. In order to increase the capacitance density and the capacitance tuning ratio (CTR), we propose a structure wherein a 25-nm-thick ferroelectric film is applied as both a gate insulator and a capacitor. The proposed structure exhibited a large capacitance density of 12.5 nF mm−2and a wide CTR of approximately 10 000. This work facilitates future integration of passive and active components for advanced highly efficient and miniaturized electronics.

Y-doped Hf–Zr–O (Y-HZO) films have been prepared by chemical solution deposition. It is shown that good ferroelectric property can be obtained for the Y-HZO film with a Y concentration of 3.2% after 800 °C crystallization annealing at a reduced pressure of 50 Pa. It is also demonstrated that the reduced pressure pre-annealing at temperatures as low as 400 °C is effective to obtain good ferroelectric properties, regardless of the crystallization annealing ambient. This is presumably because the pre-annealing under reduced pressure promotes the formation of nuclei in the orthorhombic phase.

Effects of residual oxygen in an annealing chamber on graphitization of SiC along with surface pre-treatment process have been investigated. As a pre-treatment process, SiO2 was formed on 4H-SiC(0001) substrates by thermal oxidation before graphene formation annealing. Epitaxial graphenes were formed in several O2 pressures and effects on graphitization of SiC were evaluated. It is shown that quality of graphene on SiC substrates which formed without pre-oxidation degraded by the presence of residual O2 in the chamber. It is demonstrated that SiO2 pre-oxidation films (about 10nm) were effective to prevent such degradations, for all O2 pressures that we examined in this work. In addition, at O2 pressure of 1.1x10-1Pa, with SiO2 pre-oxidation, a graphene growth rate was increased, which indicates that a certain level of O2 pressure enhances graphene growth.

Effects of catalytically generated atomic hydrogen (Cat-H) treatment on electrical properties of 10 nm thick sputtered hafnium-zirconium-oxide (HZO) films have been investigated. It is demonstrated that the Cat-H treatment to the as-deposited sputtered HZO film is effective to stabilize the metastable ferroelectric orthorhombic phase after crystallization. The enhancement of ferroelectricity by the Cat-H treatment is observed for the sputtered HZO films crystalized at a reduced pressure of 100 Pa, nitrogen and air, and the enhancement is pronounced for the films crystallized in nitrogen and air ambient. In addition, it is found that the Cat-H treatment also improves the stability against re-annealing.

To achieve graphene channel transistors which have high on/off drain current ratio and unipolar behavior of drain current – gate voltage (ID-VG) characteristics, we fabricated and characterized the top gated graphene channel transistors with n-type doped SiC source/drain regions. Graphene layer was formed on SiC by high temperature annealing in vacuum, and Al2O3 was used as a gate insulator. For the graphene channel transistor with heavily doped n-SiC source/drain regions (doping concentration ND=4.5x1019cm-3) and a 4~6ML graphene channel, ambipolar behavior was observed. On the other hand, when ND was reduced to 4.5x1018cm-3 and a thin graphene layer was used, the suppression of hole current in ID-VG curve was observed.

We have examined the effect of oxidant in metalorganic chemical vapor deposition (MOCVD) of Al2O3 gate insulator on MOSFET electrical properties. High channel mobility of 311 cm2/Vs for Al2O3/SiC MOSFET is demonstrated when the Al2O3 gate insulator is deposited on HF-treated substrate at 190oC using triethyl-aluminum (TEA) and O2 as Al source and oxidant gas, respectively. This is much higher than that of Al2O3/SiC MOSFET when Al2O3 gate insulator was deposited with TEA and H2O at the same temperature. In addition, channel mobility at high gate electric field can be improved by using O2 as oxidant gas and effective mobility of 207 cm2/Vs is obtained at SiO2 equivalent gate electric field of 1.5 MV/cm.

4H-SiC MOSFETs with Al2O3/SiC and Al2O3/SiOx/SiC gate structures have been fabricated and characterized. Al2O3 was deposited by metal-organic chemical vapor deposition (MOCVD) and the SiOx layer was formed by dry-O2 oxidation. Insertion of 1.2 nm-thickness-SiOx layer drastically improves the channel mobility of Al2O3/SiC-MOSFET and anomalously high field effect mobility (μFE) of 284 cm2/Vs was obtained. The μFE of Al2O3/SiOx/SiC-MOSFET with various SiOx thickness was investigated, and it was found that insertion of a thin SiOx layer (< 2 nm) followed by the low temperature deposition of Al2O3 results in Al2O3/SiOx/SiC-MOSFET with such a high channel mobility.

We have fabricated and characterized MOS capacitors and lateral MOSFETs using Al2O3 as a gate insulator. Al2O3 films were deposited by metal-organic chemical vapor deposition (MOCVD) at temperatures as low as 190 oC using tri-ethyl-aluminum and H2O as precursors. We first demonstrate from the capacitance – voltage (C-V) measurements that the Al2O3/SiC interface has lower interface state density than the thermally-grown SiO2/SiC interface. No significant difference was observed between X-ray photoelectron spectroscopy (XPS) Si 2p spectrum from the Al2O3/SiC interface and that from the SiC substrate, which means the SiC substrate was not oxidized during the Al2O3 deposition. Next, we show that the fabricated lateral SiC-MOSFETs with Al2O3 gate insulator have good drain current – drain voltage (ID-VD) and drain current – gate voltage (ID-VG) characteristics with normally-off behavior. The obtained peak values of field-effect mobility (μFE) are between 68 and 88 cm2/Vs.

Low temperature deposition of HfO2 films on 4H-SiC(0001) substrates by pulse introduced metalorganic chemical vapor deposition (MOCVD) using tetrakis-diethylamido-hafnium [Hf[N(C2H5)2]4, (TDEAH)] and H2O has been investigated. HfO2 films with relatively low leakage current density of 10-4 A/cm2 were obtained even at a deposition temperature as low as 190 ºC. We demonstrate that the HfO2/SiC interface, where the HfO2 was deposited at 190 ºC, has lower interface state density than a typical thermally-grown SiO2/SiC interface. It is also shown by X-ray photoelectron spectroscopy (XPS) that the HfO2/SiC structure fabricated at 190 ºC has lower SiOx count than the HfO2/SiC structure fabricated at 400 ºC.

We have fabricated Sr 2 (Ta 1 m x Nb x ) 2 O 7 (STN) films on Pt/TiO 2 /SiO 2 /Si substrates by the sol-gel technique and characterized for ferroelectric-gate FET applications. Nb composition, x, was varied from 0 to 0.5. It is found that b-axis oriented STN films were obtained when the film was annealed above 950°C. Good ferroelectric properties were obtained for the STN films with Nb compositions of 0.2 and 0.3. A remanent polarization of 0.4 w C/cm 2 was obtained for Sr 2 (Ta 0.8 Nb 0.2 ) 2 O 7 films. Metal-ferroelectric-insulator-semiconductor (MFIS) structures using Pt/STN/TiO 2 /SiON/Si systems were fabricated. Capacitance-voltage (C-V) characteristics exhibit a clear hysteresis loop due to the ferroelectric STN and a memory window of 0.4 V was obtained.

Ferroelectric films grown on Si substrates using Y2O3 buffer layers were investigated by cross-sectional high-resolution transmission electron microscopy (HRTEM). It was found that no interfacial SiO2 layer was formed when an Y2O3 layer was grown by molecular beam epitaxy (MBE) on a Si(111) substrate at 600°C, while that a SiO2 layer was formed on a Si(100) substrate under the same growth conditions. Then, ferroelectric YMnO3, SrBi2Ta2O9(SBT), and Pb(Zr,Ti)O3(PZT) films were deposited on the Y2O3/Si structures and cross-sections were observed. It was found that the interfacial SiO2 layer about 5 to 6 nm in the thickness was formed even on a Si(111) substrate after deposition of the ferroelectric film. It was also found that polygrains in PZT film were much smaller than those in SBT, although both films were formed by the same sol-gel driven method.

Metal-ferroelectrics-semiconductor field effect transistors (MFS FETs) were fabricated using ferroelectric BaMgF4 (BMF) films epitaxially grown on Si(111) substrates and their electrical characteristics were investigated. BMF films were grown on Si(111) substrates by using MBE method, and n-channel MFS FETs were fabricated on p-type Si(111) substrates by the conventional photolithographic technique. Id-Vd and Id-Vg characteristics of an fabricated MFS FET were measured, and the threshold voltage shift was observed by applying a gate voltage. It was also demonstrated that the drain current could be gradually changed by applying positive short pulses to the gate of an MFS FET.

A ferroelectric-capacitor-gate Si MOSFET which consists of an SiO2/Si MOSFET and a ferroelectric capacitor has been demonstrated. It is shown that memory functions can be obtained by connecting the ferroelectric capacitor with the gate of MOSFETs. The operation of such devices is similar to that of metal-ferroelectric-semiconductor (MFS) FETs. The large memory window or threshold voltage shift can be obtained with a ferroelectric capacitor which has a large coercive voltage. The memory effect of the device has been demonstrated by showing the drain current change by a previously applied "write" pulse at a fixed gate voltage of 0V.

PbZr x Ti 1 − x O 3 (PZT)/La 1 − x Sr x CoO 3 (LSCO) heterostructures were grown on MgO(100) substrates using the sol-gel technique and their structural and electrical properties were investigated. X-ray diffraction analysis showed that the PZT/LSCO film was polycrystalline with partial preferred (001)/(100) orientations. Fairly good ferroelectric properties of PZT were obtained when the PZT films were deposited on a well-crystallized LSCO film and were annealed at 700°C for 1 min. A typical value of the remnant polarization was 28 μC/cm. It was also found that a longer annealing time enhanced the interdiffusion of constituent elements between LSCO and PZT. It is concluded from these results that in sol-gel processing, prevention of interdiffusion and crystallinity of the LSCO electrode film are two important factors for obtaining the desirable structural and electrical properties in this system.

We demonstrate the ferroelectric behavior of PZT films grown on Si(111) substrates by using CeO 2 buffer layer. PZT (90 nm) films were prepared by electron beam assisted vacuum evaporation system and CeO 2 (27 nm) films were prepared by MBE (molecular beam epitaxy). It is found that a hysteresis is not shown in the capacitance-voltage ( c-v ) characteristics of CeO 2 /Si structures, whereas a hysteresis is obtained in the c-v plot of PZT/CeO 2 /Si structures, which is due to the ferroelectric nature of the PZT film. In addition, it is shown that the leakage current of PZT/CeO 2 /Si is as low as 10 A/cm at 8 V.

Ferroelectric BaMgF 4 films have been grown on GaAs substrates with and without an AlGaAs buffer layer for metal-ferroelectric-semiconductor field effect transistor (MFSFET) applications. It is shown that the temperature range of 530-570°C is suitable to grow the (140)-oriented BaMgF 4 films on GaAs. Furthermore, it is demonstrated that the AlGaAs buffer layer is effective to reduce the leakage current. Capacitance-voltage ( c-v ) characteristics of Al/BaMgF 4 /AlGaAs/n-GaAs/n-GaAs(100) structures show a hysteresis loop with a counterclockwise trace, demonstrating the ferroelectric nature of the BaMgF 4 film. On the other hand, the BaMgF 4 film directly grown on GaAs substrates has clockwise-hysteresis loops due to the charge injections. It is also shown that the remanent polarization estimated from the polarization-electric field ( P-E ) characteristics is as large as 1.2 μC/cm.

Pb(ZrxTi1-x)O3 (PZT) thin films have been prepared on Pt/MgO substrates by vacuum evaporation technique using PbO and ZrO2/TiO2 pellets as source materials. Good quality PZT can be obtained by employing Two-step evaporation method, where only PbO is evaporated at first before the PZT evaporation. Remanent polarizations of 17-29 μC/cm2 and coercive fields of 45-126 kV/cm are obtained.

Ferroelectric BaMgF 4 films have been grown on AlGaAs/GaAs(100) high-electron-mobility transistor (HEMT) structures. BaMgF 4 films in which the direction of spontaneous polarization has a finite angle to the substrate surface can be obtained on the HEMT structure at growth temperatures of 500-600°C. However, it is shown that the growth temperature is limited to about 550°C, because the AlGaAs/GaAs interface becomes disordered by the diffusion of Mg atoms into the HEMT structure when the growth temperature is 600°C.

Stability of ferroelectricity in hafnium-zirconium oxide (HZO) films deposited by sputtering and chemical solution deposition (CSD) has been investigated. After confirming the ferroelectricity of both sputtered HZO and CSD yttrium-doped HZO (Y-HZO) films, indium-tin-oxide (ITO) was deposited by sputtering on sputtered HZO or CSD Y-HZO layer to fabricate metal-ferroelectric-semiconductor (MFS) structure. It was found that the sputtered HZO films in the MFS structure became paraelectric after re-annealing in N2which was confirmed by both X-ray diffraction pattern and electrical measurements. On the other hand, the CSD Y-HZO films showed ferroelectric nature even after re-annealing with a negligible monoclinic phase.

The electrical and patterning properties of direct imprinted indium oxide (In2O3) and indium tin oxide (ITO) precursor gel films have been studied. The electrical properties of the imprinted films have also been compared with the electrical properties of non-imprinted films. In2O3 and ITO have almost the same type of solutes in solution but In2O3 shows better patterns than ITO, that is, the addition of tin to In2O3 causes the patterns to degrade because ITO has a lower tan d during viscoelastic measurements than In2O3. In addition, the electrical properties (i.e. Hall mobility and carrier concentration) of In2O3 were affected by the direct imprinting process while the effects were not pronounced for ITO films.

We report on a new fabrication process for thin-film transistors (TFTs) with a new structure and a new operation principle. In this process, both the channel and electrode (source/drain) are formed simultaneously, using the same oxide material, using a single nano-rheology printing (n-RP) process, without any conventional lithography process. N-RP is a direct thermal imprint technique and deforms oxide precursor gel. To reduce the source/drain resistance, the material common to the channel and electrode is conductive indium-tin-oxide (ITO). The gate insulator is made of a ferroelectric material, whose high charge density can deplete the channel of the thin ITO film, which realizes the proposed operation principle. First, we have examined the n-RP conditions required for the channel and source/drain patterning, and found that the patterning properties are strongly affected by the cooling rate before separating the mold. Second, we have fabricated the TFTs as proposed and confirmed their TFT operation.

We successfully fabricated ferroelectric gate thin film transistors (FGTs) using solution-processed (Bi,La)4Ti3O12(BLT)/Pb(Zr,Ti)O3(PZT) stacked films and an indium--tin oxide (ITO) film as ferroelectric gate insulators and an oxide channel, respectively. The typical n-type channel transistors were obtained with the counterclockwise hysteresis loop due to the ferroelectric property of the BLT/PZT stacked gate insulators. These FGTs exhibited good device performance characteristics, such as a high ON/OFF ratio of $10^{6}$, a large memory window of 1.7--3.1 V, and a large ON current of 0.5--2.5 mA. In order to investigate interface charge trapping for these devices, we applied the conductance method to MFS capacitors, i.e., Pt/ITO/BLT/PZT/Pt capacitors. As a result, the interface charge trap density ($D_{\text{it}}$) between the ITO and BLT/PZT stacked films was estimated to be in the range of $10^{-11}$--$10^{-12}$ eV-1cm-2. The small $D_{\text{it}}$ value suggested that good interfaces were achieved.

We demonstrate ferroelectric gate thin-film transistors (Fe-TFTs) with very thin (60, 110 nm) ferroelectric polymer poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] and amorphous indium gallium zinc oxide (a-IGZO) as the channel layer on a glass substrate. First, we confirm the basic ferroelectric properties of the 60- and 110-nm-thick-P(VDF-TrFE) films. Next, we fabricate Fe-TFTs with the Al/P(VDF-TrFE) (60 and 110 nm)/a-IGZO (10 nm) top-gate structure. Excellent electrical characteristics are demonstrated and nonvolatile memory function is confirmed with memory windows of 2.3 and 4.3 V, when the thicknesses of P(VDF-TrFE) were 60 and 110 nm, respectively. In particular, the Fe-TFTs with 60-nm-thick-P(VDF-TrFE) film were operated under 8 V.

We demonstrate ferroelectric gate thin-film transistors (Fe-TFTs) with very thin (60, 110 nm) ferroelectric polymer poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] and amorphous indium gallium zinc oxide (a-IGZO) as the channel layer on a glass substrate. First, we confirm the basic ferroelectric properties of the 60- and 110-nm-thick-P(VDF-TrFE) films. Next, we fabricate Fe-TFTs with the Al/P(VDF-TrFE) (60 and 110 nm)/a-IGZO (10 nm) top-gate structure. Excellent electrical characteristics are demonstrated and nonvolatile memory function is confirmed with memory windows of 2.3 and 4.3 V, when the thicknesses of P(VDF-TrFE) were 60 and 110 nm, respectively. In particular, the Fe-TFTs with 60-nm-thick-P(VDF-TrFE) film were operated under 8 V.

We have fabricated inorganic ferroelectric-gate thin-film transistors (FGTs) using only a chemical solution deposition (CSD) process. All layers, including the LaNiO3(LNO) gate electrode, Pb(Zr,Ti)O3(PZT) ferroelectric-gate insulator, indium--tin-oxide (ITO) source/drain electrodes, and ITO channel, were formed on a SrTiO3(STO) substrate by the CSD process. We obtained a local epitaxially grown PZT/LNO perovskite heterostructure with good crystalline quality and no interfacial layer. The fabricated FGT exhibited typical n-channel transistor operation, with a counterclockwise hysteresis loop due to the ferroelectric nature of the PZT-gate insulator, and also exhibited good drain current saturation in output characteristics. These properties are equivalent to or better than those obtained with FGTs fabricated by means of conventional vacuum processes. The obtained on/off current ratio, memory window, and subthreshold voltage swing were about $10^{6}$, 2.5 V, and 357 mV/decade, respectively.

A thermal press treatment was introduced in the sol--gel process of PbZrxTi1-xO3(PZT) thin films for the first time and the crystalline and electrical characteristics of the PZT films were investigated. The thermal press treatment was applied to the amorphous PZT gel film before crystallization annealing. It is found that the crystalline orientation and grain size of the PZT film fabricated with the thermal press treatment are different from those of the film fabricated by the conventional sol--gel process without the thermal press treatment, even though the crystallization conditions are exactly the same. It is demonstrated that the electrical properties, especially leakage current density and breakdown field, are significantly improved for the PZT film fabricated with the thermal press treatment. Furthermore, we also demonstrate that the fatigue property is improved by introducing the thermal press treatment.

This paper describes a method for utilizing an excimer laser to improve the characteristics of InGaZnO4 (IGZO) thin-film transistors (TFTs). IGZO-TFTs fabricated at room temperature are irradiated with an excimer laser to raise the temperature of the IGZO films for only a very short time, some tens of ns. The ON current of an irradiated IGZO-TFT is more than one order of magnitude higher than that of an un-irradiated TFT. This method is promising for achieving high performance IGZO-TFTs on plastic substrates because the thermal damage to substrates will be much less than that which would result from furnace annealing.

This paper describes a method for utilizing an excimer laser to improve the characteristics of InGaZnO4(IGZO) thin-film transistors (TFTs). IGZO-TFTs fabricated at room temperature are irradiated with an excimer laser to raise the temperature of the IGZO films for only a very short time, some tens of ns. The ON current of an irradiated IGZO-TFT is more than one order of magnitude higher than that of an un-irradiated TFT. This method is promising for achieving high performance IGZO-TFTs on plastic substrates because the thermal damage to substrates will be much less than that which would result from furnace annealing.

Metal-ferroelectric-(metal-)insulator-semiconductor (MF(M)IS) structures are fabricated and characterized using (Pb, La)(Zr0.3Ti0.7)O3(PLZT) and Y2O3films. Y2O3buffer layers are epitaxially grown on Si(111) substrates by molecular beam epitaxy and ferroelectric PLZT films are formed on (Pt/)Y2O3/Si by the sol-gel technique. It was found that the Al/Y2O3/Si MIS structure has a low leakage current of less than 10-8A/cm2. The capacitance-voltage (C-V) characteristics of the PLZT/Y2O3/Si MFIS structure exhibit a hysteresis loop due to the ferroelectricity of the PLZT film with a memory window of 1 V. On the other hand, the memory window of the Pt/PLZT/Pt/Y2O3/Si MFMIS structures is significantly improved.

A metal-ferroelectric-metal-oxide-semiconductor field effect transistor (MFMOS-FET) with a Pt/SrBi2Ta2O9/Pt/Ti/SiO2/Si structure was fabricated on a silicon-on-insulator (SOI) structure in order to improve the memory retention characteristics of ferroelectric neuron circuit. The area ratio of MOS capacitor to MFM capacitor was changed from 3 to 15 so that charge quantities induced in both capacitors were optimized. It was found that the memory operations and retention characteristics were considerably improved in the fabricated MFMOS-FET with an area ratio larger than 10, compared with those of the MFSFET previously fabricated using a Pt/SrBi2Ta2O9/Si structure. Next, a pulse frequency modulation (PFM)-type neuron circuit was fabricated using the MFMOS-FET and a CMOS Schmitt-trigger oscillator as a synapse and a neuron, respectively, and it was found that the oscillation frequency of the circuit remained almost unchanged over a period of 1 h.

Nonvolatile memory operations of p-channel metal-ferroelctric-insulator-semiconductor (MFIS)- and metal-ferroelectric-metal-insulator-semiconductor (MFMIS)-FETs using ferroelectric SrBi2Ta2O9(SBT) film and SrTa2O6(STA)/SiON stacked buffer layer have been demonstrated. It is determinded that the Al/STA/SiON/Si structure with a SiO2equivalent thickness of 3.7 nm has low leakage current of 10-8A/cm2. The memory window of 1.1 V is obtained for Pt/SBT/STA/SiON MFIS-FETs, whereas Pt/SBT/Pt/STA/SiON/Si MFMIS-FETs have memory windows as large as 3.0 V when the area ratio SM/SFis 3.8 or 5.9. Furthermore, it is also demonstrated that by reducing the metal-ferroelectric-metal (MFM) capacitor area, significant improvement of data retention characteristics can be achieved. The drain current on-off ratio remains at more than three orders of magnitude even after an elapse of 10 h.

A liquid-delivery metalorganic chemical vapor deposition (MOCVD) apparatus for preparing SrBi2Ta2O9(SBT) thin films was designed and set up. For the preparation of SBT thin films, a double alcoholate source, Sr[Ta(OC2H5)6]2, was used for supplying Sr and Ta atoms with a stoichiometric composition, while Bi(C6H5)3was used for supplying Bi atoms. In the experiment, variation of the film composition with the deposition temperature and source-supply mol ratio was primarily investigated. It was found that the Bi/Ta mol ratio in the films varied with the deposition temperature and became smaller at lower deposition temperatures. It was also found that the Sr/Ta mol ratio was considerably smaller than stoichiometry above 500°C, probably because of the dissociation of Sr[Ta(OC2H5)6]2. It was ascertained that a 200-nm-thick SBT thin film with the Sr/Ta mol ratio of about 0.4, which was deposited at 350°C and subsequently annealed in O2atmosphere at 750°C for 30 min, exhibited ferroelectricity. The dielectric constant of the film was about 120. Remanent polarization and coercive field at 10 V were 3.8 µC/cm2and 73 kV/cm, respectively. However, the leakage current density was found to be as high as the order of 10-4A/cm2at 3 V. It is speculated from atomic force microscope (AFM) observation of the surface roughness of the film that the origin of the high leakage current density is the existence of local high electric field spots in the film.

The adaptive-learning function was successfully demonstrated in a neuron circuit using a metal/ferroelectric/semiconductor field effect transistor (MFSFET). The polarization direction of the ferroelectric gate film (SrBi2Ta2O9) of MFSFET was gradually reversed by applying a number of input pulses with a sufficiently short duration of 20 ns. Consequently, the S-D (source-drain) resistance of MFSFET was gradually changed, and the output pulse frequency of the neuron circuit was modulated by the number of input pulses.

Electrical properties of ferroelectric BaMgF4films grown on AlGaAs/GaAs(100) high-electron-mobility transistor (HEMT) structures are investigated. It is shown that a spontaneous polarization of 1.3 µC/cm2and a coercive field of 200 kV/cm are obtained from polarization vs electric field (P-E) hysteresis measurements for mainly (140)-oriented BaMgF4films. In addition, a threshold shift (memory window) as large as 1.2 V is demonstrated in capacitance-voltage (C-V) hysteresis measurements for a BaMgF4(140)/HEMT structure in which the growth temperature of the BaMgF4film is about 550°C. This work indicates that the suitable growth temperature of BaMgF4films on the HEMT structure is 550°C.

Lead-zirconate-titanate (PbZrxTi1-xO3:PZT) films were epitaxially grown on Si(111) substrates using Y2O3buffer layers. Y2O3layers were prepared in a molecular beam epitaxy (MBE) apparatus with a single electron beam gun, while PZT films were prepared in a vacuum evaporation chamber with both a crucible and an electron beam gun. It was found from in situRHEED observation that Y2O3layers grew epitaxially on Si(111) substrates. It was also found from X-ray diffraction analysis that strongly (101)-oriented PZT films grew on the Y2O3/Si(111) structures at a substrate temperature of 700°C. Metal-ferroelectric-insulator-semiconductor(MFIS) capacitors were fabricated using this structure, and capacitance-voltage (C-V) curves showed a memory window of about 2.6 V, which is considered to be due to the ferroelectric nature of the PZT film.

Switching characteristics of ferroelectric PbZrxTi1-xO3thin films prepared by the sol-gel technique have been studied for "adaptive learning" metal-ferroelectric-semiconductor field effect transistor (MFSFET) applications. It is demonstrated that by applying positive short pulses to the metal-ferroelectric-metal (MFM) capacitors, the polarization of PZT films can be gradually reversed. We have also measured the switching characteristics by applying various input voltages. Experimentally measured current responses and polarization changes can be well fitted by the Kolmogorov-Avrami theory by taking into account the voltage dependence of the reversed polarization.

Carbon-doped InxGa1-xAs layers (x=0?0.96) were grown by metalorganic molecular beam epitaxy (MOMBE) using trimethylgallium (TMG), solid arsenic (As4) and solid indium (In) as sources of Ga, As and In, respectively. The growth temperature and the indium beam flux strongly affect carrier concentration, and the growth temperature also affects the indium molar fraction of the InxGa1-xAs layers grown even with the fixed indium beam flux. The hole concentration decreases with increasing indium molar fraction from 0 to 0.8, and then the conduction type changes from the p to n type at x=0.8. Hole concentrations of 1.0×1019and 1.2×1018cm-3are obtained for x=0.3 and 0.54, respectively. These values are significantly higher than those reported for carbon-doped InxGa1-xAs by MBE.

Maximum carrier concentrations reported in the literature are compared with the respective Fermi level stabilization positions for various semiconductors. It is shown that heavy n-type (p-type) doping is obtainable for a semiconductor whose Fermi level stabilization position is located near the conduction (valence) band edge.

We report the crystalline quality and electrical properties of PbZrxTi1-xO3(PZT) films grown on Si substrates with a SrTiO3(STO) buffer layer. STO buffer layers and PZT films were formed on Si substrates by the electron-beam assisted vacuum evaporation technique and the sol-gel technique, respectively. It is shown that by using a thin (8 nm) metal Sr layer or fluoride ( SrF2, CaF2) predeposition layers prior to the STO deposition, which reduces the SiO2layer at the Si surface, highly oriented STO and PZT thin films can be grown on Si(100) and (111) substrates. Crystalline orientation of the PZT films strongly depends on the crystalline orientation of the STO buffer layers. It is also shown that the full width at half-maximum (FWHM) values of X-ray diffraction (XRD) peaks from PZT films are strongly related to those of STO buffer layers. Furthermore, the capacitance-voltage characteristics and current response measurements indicate the ferroelectric nature of PZT films grown on STO-covered Si substrates.

A GaAs pseudo-heterojunction bipolar transistor with a heavily carbon-doped base grown by metalorganic molecular beam epitaxy was fabricated, and the highest dc current gain of 1.7 was obtained, which evidences band-gap narrowing in the base. However, hole injection from the base to the emitter still cannot be ignored, and the use of a heavily carbon-doped InGaAs base is proposed to improve transistor characteristics.

Metalorganic molecular beam epitaxial (MOMBE) growth of GaAs and (GaAl)As using triethylgallium (TEG) and triethylaluminum (TEA) has been studied. N-GaAs/p-GaAs multi-layer structures were prepared by applying an alternating ionization voltage to hydrogen. Single-crystal Ga1-xAlxAs ternary alloy with good surface mophology was successfully grown by introducing TEA as an Al source. The epitaxial layers typically showed p-type conduction with a carrier concentration of more than 1018cm-3, this being due to residual carbon. A (GaAl)As/GaAs multiquantum well (MQW) heterostructure was fabricated by switching TEA and it was observed that the photoluminescence peak energies from the MQW structures were shifted to the higher energy position. Furthermore, selective growth of GaAs and (GaAl)As on a partly SiO2masked GaAs substrate was investigated. In the MOMBE growth of (GaAl)As, polycrystalline film was deposited on the SiO2masked region, while no deposition took place in the growth of GaAs.

We have evaluated the electron mobility in BaMgF4/AlGaAs/GaAs(100) high-electron-mobility transistor (HEMT) structures using a contactless mobility measurement system. It has been found that the HEMT structure can be prevented from deteriorating when the BaMgF4layer is properly deposited, and that dependence of the electron mobility on the N-AlGaAs layer thickness is explained using a simple parallel conduction theory. It has also been found that the electron mobility in the structures is decreased from 6300 cm2/(V·s) to 3300 cm2/(V·s) at room temperature as the rmBaMgF4growth temperature is increased from 550° C to 650° C.

Partial switching in ferroelectric PbZrxTi1-xO3(PZT) thin films has been studied for adaptive-learning metal-ferroelectric-semiconductor field-effect transistor (MFSFET) applications. In particular, the effects of film quality on adaptive-learning processes in ferroelectric PZT thin films are discussed. Dimensionality factor nof the ferroelectric domain growth is estimated to be 1.3-1.4 for sol-gel grown PZT films and 2.0-2.1 for vacuum-evaporated materials. It is shown that this discrepancy results in the difference of the adaptive-learning processes. It is also demonstrated that the learning process in PZT films can gradually proceed by applying the short input pulses.