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In this article, we explore different device and standard cell architectures for scaling the Germanium fin field-effect transistor (FinFET) and nanosheet (NS) at the sub-5-nm node. It is demonstrated that the Germanium device provides approximately 70% improvement in drive current and $3.4\times $ less device resistance. The main concern for Germanium devices remains the high leakage current due to the gate-induced drain leakage, which limits their usage to high-speed applications. Overall, Germanium devices require fewer boosters than silicon to scale beyond the 5-nm node. Contact resistivity is found to be a critical knob for Germanium and it can be relaxed to 3e $- 9\,\,\Omega $ -cm2 to meet the power and performance targets for the sub-5-nm node. Moving to the NS helps in relaxing this constraint further.

With each new node, cost and complexity of logic technology increases while being challenged to provide the historical expected improvement in performance. This paper reviews the latest trends and advances in technology to enable logic scaling. Dimensional scaling, enabled by EUV lithography, will continue with advances in multi-patterning. Higher costs of EUV multi-patterning will be mitigated by high (0.55) numerical aperture (NA) EUV simplifying the patterning and potentially leading to higher yield. Logic standard cell scaling below 6-track (6T) with adequate drive current per footprint will require adoption of Gate-All-Around (GAA) device architectures, like nanosheets, along with scaling boosters like buried power rails (BPR) and semi-damascene metal integration scheme with air-gaps. Scaling below 5-track (5T) will require new compact device architectures like complementary FETs (CFETs) and alternate intra-cell interconnect layouts. Slowing SRAM scaling can also benefit from migration to BPR, forksheets and CFETs. Channels formed from 2D materials can theoretically enable gate length (L g ) and contacted poly pitch (CPP) scaling. Several new material innovations will be needed to enable 2D atomic channel transistors. Changing our view from circuits to systems, 3D integration techniques will continue to enable subsystem scaling like cache partitioning of SoCs to improve memory access. Finally, a methodology to estimate the environmental impact of technology scaling choices is proposed.

© 2018 IEEE. Carbon Nanotube Field-Effect Transistors (CNFETs) are highly promising to improve the energy efficiency of digital logic circuits. Here, we quantify the Very-Large-Scale Integrated (VLSI) circuit-level energy efficiency of CNFETs versus advanced technology options (ATOs) currently under consideration [e.g., silicon-germanium (SiGe) channels and progressing from today's FinFETs to gate-all-around nanowires/nanosheets]. We use industry-practice physical designs of digital VLSI processor cores in future technology nodes with millions of transistors (including effects from parasitics and interconnect wires) and technology parameters extracted from experimental data. Our analysis shows that CNFETs are projected to offer 9× energy-delay product (EDP) benefit (∼3× faster while simultaneously consuming ∼3× less energy) compared to Si/SiGe FinFET. The ATOs provide

In this paper, lateral gate-all-around nano-sheet transistors (NSH-FETs) are explored from intrinsic performance to dc and ring oscillator (RO) benchmark compared with FinFETs and nanowire transistors (NW-FETs) for sub-7-nm node. The band structure calculated technology computer aided design results show comparable intrinsic performance to FinFETs at same channel cross section. On top of that, dc and RO are evaluated by taking into account electrostatics, parasitic components, and layout configurations. The NSH-FETs show an advantage in drive current with the NSH width but their RO performance is limited by the device capacitance. The multiple narrow NSH-FET shows ~5% higher drive current compared to the NW-FET at similar subthreshold swing, allowing heavier capacitive loaded circuit. In addition, NSH-FETs can provide the device design freedom from aggressive fin pitch scaling.

The fine balance between dipole-field energy and anion drift force defines the switching mechanism during polarization reversal: for the first time we show that only Pbcm mechanism obeys the ferroelectric switching physics, whereas P4(2)/nmc (or any other) mechanism does not. However, with lower energy barrier, it represents an important antiferroelectric mechanism. Constraints relaxation can lead to 90 degrees polarization rotation (domain deactivation). Intrinsically, the Si/VO-doping can switch faster than undoped HfO2 or HfZrOx. Theoretical Arrhenius model / intrinsic material switching (DFT) overestimates the switching speed extracted from experiments.

We report, for the first time, on a SPICE simulation study of the circuit-level power-performance impact of device traps in a state-of-the-art III-V heterojunction tunnel FET (TFET). First, the individual parasitic effects of junction bulk traps and oxide interface traps are incorporated in a compact model and validated against measurement-calibrated TCAD data, where we propose an analytical formulation for trap-assisted tunneling at the heterojunction and account for the oxide interface charge with a look-up table. Then, the model is used in SPICE simulations on a ring oscillator test bench to predict the impact of traps on logic circuits. It is found that bulk and oxide traps in TFET together cause up to ~5x iso-frequency energy penalty in the desired low-supply-voltage domain (≤0.50V), of which oxide traps dominate at high switching activity while bulk and oxide traps contribute comparably when switching is less active. This study quantitatively suggests that trap reduction is the key to the enablement of the full benefit of TFET. ispartof: 2018 IEEE S3S Conference Final Proceedings ispartof: IEEE SOI-3D-Subthreshold Microelectronics Technolology Unified Conference (S3S) location:Burlingame, CA, USA date:15 Oct - 17 Oct 2018 status: published

Negative Bias Temperature Instability (NBTI) is one of the major time-dependent degradation mechanisms that impact the reliability of advanced deeply scaled CMOS technologies. NBTI can cause workload-dependent shifts on a transistor's threshold voltage ( V TH ), and performance during its lifetime. This study presents a comparison of the NBTI aging on adder architectures and ring oscillators in the downscaling technology nodes. The first part of the study focuses on the NBTI-induced performance degradation of 32-bit adders (one of the most fundamental block of a processor's arithmetic logic unit) from the points of architectural topology and workload dependency in the planar technologies (i.e. commercial 28 , 45 , 65 nm nodes), while the second part investigates the energy-delay product degradation of ring oscillators beyond the planar nodes (i.e. research-grade 14 , 10 , 7 nm FinFET technology nodes for several FET channel materials, e.g. Si, SiGe, Ge, InGaAs). Results show the tight coupling between the NBTI aging and the architectural topology, run-time workload, and technology choice.

In this paper, we compare the performances of FinFETs, lateral gate-all-around (GAA) FETs, and vertical GAAFETs (VFETs) at 7-nm node dimensions and beyond. Comparison is done at ring oscillator level accounting not only for front-end of line devices but also for interconnects. It is demonstrated that FinFETs fail to maintain the performance at scaled dimensions, while VFETs demonstrate good scalability and eventually outperform lateral devices both in speed and power consumption. Lateral GAAFETs show better scalability with respect to FinFETs but still consume 35% more energy per switch than VFETs if made under 5-nm node design rules.

The continued physical feature size scaling of CMOS transistors is experiencing asperities due to several factors (physical, technological, and economical), and it is expected to reach its boundary in the coming years. Sequential-3D (S3D) integration has been perceived as a promising alternative to continue the benefits offered by semiconductor scaling. This paper addresses the different variants of S3D integration and potential challenges to achieve a realizable solution. We analyze and quantify the benefits observed due to sequential scaling at a die level.

This paper discusses SRAM scaling beyond the 5nm technology node and highlights the fundamental scaling limits due to FinFET and Gate all-around (GAA) technology. To compensate for expected gate pitch scaling slowdown below 42nm, several scaling boosters are needed to reduce the cell height. However, limited scaling benefits can be achieved in FinFET and GAA technology. Therefore, a novel vertically stacked lateral nanosheet architecture using a forked gate structure is proposed showing superior performance and area scaling compared to FinFET and GAA devices. Moreover, limited additional processing complexity can be achieved. The Fork architecture allows 20% SRAM area scaling at isoperformance and 30% performance increase at iso-area compared to FinFET beyond 5nm technology node.

In this paper, standard cell design for iN7 CMOS platform technology targeting the tightest contacted poly pitch (CPP) of 42 nm and a metal pitch of 32 nm in the FinFET technology is presented. Three standard cell architectures for iN7, a 7.5-Track library, 6.5-Track library, and 6-Track library have been designed. Scaling boosters are introduced for the libraries progressively: first an extra MOL layer to enable an efficient layout of the three libraries starting with 7.5-Track library; second, fully self aligned gate contact is introduced for 6.5 and 6-Track library and third, 6-Track cell design includes a buried rail track for supply. The 6-Track cells are on average 5% and 45% smaller than the 6.5 and 7.5-Track cells, respectively.

Si1-xGex-channel pFETs can combine enhanced intrinsic performance with a threshold voltage shift, therefore this technology possibly facilitates the use of high-k/metal gate stacks in high-performance applications. This review presents imec's work on a new device concept using Si1-xGex-channels, the implant-free quantum well transistor, that can additionally provide improved short-channel scalability, as well as further performance enhancement when compared to conventional silicon and Si1-xGex-channel pFETs. Furthermore, circuit simulations of Si1-xGex-channel pFETs indicate that this technology shows even more enhanced potential at reduced supply voltages, and also in circuits that allow operation at lower electric fields such as stacked transistors. Finally it is demonstrated that the layout sensitivity of Si1-xGex-channel pFETs is an important concern, especially for variations of the device width. The effectiveness of another stress technique, Si1-xGex Source/Drain, is shown to be decreased when used in combination with Si1-xGex-channel pFETs.

This paper presents a pseudo-2-D surface potential model for the double-gate tunnel field-effect transistor (DG-TFET). Analytical expressions are derived for the 2-D potential, electric field, and generation rate, and used to numerically extract the tunneling current. The model predicts the device characteristics for a large range of parameters and allows gaining insight on the device physics. The depletion regions induced inside the source and drain are included in the solution, and we show that these regions become critical when scaling the device length. The fringing field effect from the gates on these regions is also included. The validity of the model is tested for devices scaled to 10-nm length with SiO2 and high-? dielectrics by comparison to 2-D finite-element simulations.

Suspended gate field-effect transistors (SG-FETs) with switching gates are interesting as digital logic switches because of their high I on/I off current ratio and their infinite subthreshold slope. However, the limits of scalability of the SG-FETs are still unclear. This paper investigates two effects that could limit scaling: the dielectric charging and the dielectric roughness. To do so, a surface-potential-based model for suspended gate transistors with a mechanically switching gate is presented and validated using experimental data. Devices fabricated in a standard complimentary metal-oxide-semiconductor process are used for the model assessment. The model reproduces the effect of a fixed charge and the effect of a nonideal contact of the gate after pull-in. We show that, at the device dimensions required to follow the International Technology Roadmap for Semiconductors, these effects will be critical.

Standard-cell design, technology choices, and place and route (P&R) efficiency are deeply interrelated in CMOS technology nodes below 10 nm, where lower number of tracks cells and higher pin densities pose increasingly challenging problems to the router in terms of congestion and pin accessibility. To evaluate and downselect the best solutions, a holistic design-technology co-optimization approach leveraging state-of-the-art P&R tools is thus necessary. We adopt such an approach using the imec N7 technology platform, with contacted poly pitch of 42 nm and tightest metal pitch of 32 nm, by comparing post P&R area of an IP block for different standard cell configurations, technology options, and cell height. Keeping the technology node and the set of ground rules unchanged, we demonstrate that a careful combination of these solutions can enable area gains of up to 50%, comparable with the area benefits of migrating to another node. We further demonstrate that these area benefits can be achieved at isoperformance with >20% reduced power. As at the end of the CMOS roadmap, conventional scaling enacted through pitch reduction is made more and more challenging by constraints imposed by lithography limits, material resistivity, manufacturability, and ultimately wafer cost, the approach shown herein offers a valid, attractive, and low-cost alternative.

In this paper, we first outline the impact of Bias Temperature Instability (BTI) on the transistor threshold voltage as a function of time and the gate oxide field. Subsequently, the correlation between time-zero and time-dependent variability is described. A combined distribution encompassing both contributions with their relative weights is derived. Finally, circuit-level insights on the BTI impact are given based on case study simulations of Ring Oscillators (ROs) at commercial-grade 28nm planar and research-grade 14, 10, 7nm FinFET technology nodes for several FET channel materials (e.g. Si, SiGe, Ge, InGaAs).

Design-Technology co-optimization becomes a key knob to enable CMOS scaling. In this work we evaluate the technology options including lithography options as well as device options that are considered to enable N10 scaling by exploring their impact on representative designs such as standard cells, SRAM and analog contexts. This paper illustrates that the design angle needs to be considered early in the development of a technology node. This design assessment and decisions start from lithography constraints and options to power/performance, area and cost, all of which create the Design-Technology Co-Optimization space.

As CMOS technology goes into the nanoscale regime, the impact of layout on the device performance becomes increasingly important. In this paper, we propose a physics-based analytical model for Layout Dependent Effects (LDE) due to shallow trench isolation (STI) stress in 28 nm technology using “gate-last” process (Replacement Gate — RMG). The impact of active size and active width are considered and the model links between stress and device parameters such as the mobility and threshold voltage. The model is validated with experimental data. In addition, we investigate the impact of embedded Silicon-Germanium source/drain (eSiGe S/D) stressors in PMOS. Stronger mobility degradation is predicted for small width devices once eSiGe S/D is used. It results in a larger drop of normalized current (μA/μm) (−16%) once compared to transistors without eSiGe (−7%).

Standard-cell design and characterization are presented for 7-nm CMOS platform technology targeting low-power and high-performance applications with the tightest contacted poly pitch of 42 nm and a metallization pitch of 32 nm in the FinFET technology. Two standard-cell architectures for 7 nm, a 9-track library and a 7.5-track library have been designed, introducing an extra middle-of-line layer to enable an efficient layout of the 7.5-track cells. The 7.5-track cells are on average smaller than the 9-track cells. With the strict design constraints imposed by self-aligned quadruple patterning and self-aligned double patterning, careful design and technology co-optimization is performed.