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We report on recent progress and next steps in the design of the proposed MATHUSLA Long Lived Particle (LLP) detector for the HL-LHC as part of the Snowmass 2021 process. Our understanding of backgrounds has greatly improved, aided by detailed simulation studies, and significant R&D has been performed on designing the scintillator detectors and understanding their performance. The collaboration is on track to complete a Technical Design Report, and there are many opportunities for interested new members to contribute towards the goal of designing and constructing MATHUSLA in time for HL-LHC collisions, which would increase the sensitivity to a large variety of highly motivated LLP signals by orders of magnitude., Contribution to Snowmass 2021 (EF09, EF10, IF6, IF9), 18 pages, 12 figures. v2: included additional endorsers. v3: updated affiliations. v4: added missing contributors as authors

Using the INRA – University of Minnesota porcine 7000 Rad Radiation Hybrid panel (IMpRH) containing 118 clones, porcine cellular retinol binding protein gene 1 (RBP1) and plasma retinol binding protein gene 4 (RBP4) were assigned to porcine chromosomes 13 and 14, respectively. The mRNA distributions of the two genes in adult Wuzhishan pig tissues (lung, skeletal muscle, spleen, heart, stomach, large intestine, lymph node, small intestine, liver, brain, kidney and fat) were examined. One single nucleotide polymorphism (SNP) was identified in Laiwu, Wuzhishan, Guizhou, Bama pig breeds and a Tongcheng experimental population and analysed using a polymerase chain reaction–restriction fragment length polymorphism (PCR–RFLP) method. Significant associations were found between different genotypes of A/G156 and maximum carcass length (LM), minimum carcass length (LN), haemoglobin (HGB), mean corpuscular volume haemoglobin (MCH), and day to slaughter weight (age) traits in the Tongcheng experimental population. This SNP locus might be used as a genetic marker in pig breeding and production.

To solve the problem of congestion which often occurs in the process of the large data transmission in large-scale wireless senator networks, a multipath routing protocol based on congestion control mechanism implemented by cross-layer design concept is proposed. Realizing the multipath routing protocol on the basis of AODV protocol, congestion control mechanism with active congestion avoidance, real-time detection and alleviative congestion is implemented by applying interaction information of cross-layer design between MAC layer and Routing layer. The simulation results show that the proposed multipath routing protocol with congestion control mechanism has some advantages in packet delivery ratio, end-to-end delay and normalized overheads. The proposed protocol can ensure the reliability and validity of service, and save energy consumption to prolong the working lifetime of wireless sensor networks.

Wavelength reuse techniques for bidirectional ultra-wide band (UWB) over fiber (UWBoF) networks are presented. The downstream optical signal from the central station (CS) is reused for upstream data transmission with the original data erased at the base station (BS). Two wavelength reuse schemes for the generation of a clear optical carrier at the BS are theoretically analyzed and experimentally demonstrated. In the first scheme, the wavelength reuse is based on phase-modulation to intensity-modulation (PM-IM) conversion and destructive interferencing using a polarization modulator (PolM) and a fiber Bragg grating (FBG). A theoretical analysis is performed which is verified by an experiment. In the second scheme, the wavelength reuse is based on injection locking of a Fabry–Pérot laser diode (FP-LD) and polarization multiplexing. The UWB injection signal contributes to better BERs of both downstream and upstream services and a lower power penalty cause by the wavelength reuse of the whole system than the baseband signal. A bidirectional point-to-point transmission of over a 25-km single-mode fiber (SMF) using a single wavelength from the CS in each scheme is demonstrated.

In February 2002, the Federal Communications Commission allocated huge frequency band (3.6 - 10.1 GHz) for UWB communication. Now many wireless communication experts are considering using a variety of techniques to utilize the huge bandwidth. Based on the fact that the large bandwidth of UWB waveform significantly increases the ability of the receiver to resolve the different reflections in the channel, most receivers are basically developed from the RAKE receiver [S. Roy et al., Feb 2004]. This paper proposes a modified receiver for UWB communication system. The receiver is composed of a symbol detector and a channel decoder separated by a deinterleaver. The principle of turbo-code and an iterative detecting-decoding process is applied in the receiver.

An op-amp with a push-pull output stage for infrared focal plane array (IRFPA) readout integrated circuit (ROIC) is described in this paper. It works in the class AB mode with little die area. The op-amp is simulated by the SMIC 0.35-/spl mu/m CMOS process. The circuit is designed to operate from a single 5 V power and drive a capacitive load of 15 pF. The unity gain-bandwidth (GBW) is 30 MHz. the rising slew rate (SR) 34 V/s. and the falling slew rate (SR-) 39 V/s. The common-mode input and the output swing are almost 5 V.

A novel dual-window readout structure is presented in this paper. The ROIC with this structure can work in two modes: normal mode and windowing mode. The most special feature is that ROIC can readout two sub-arrays synchronously in windowing mode. Furthermore, the positions and sizes of these sub-arrays can be specified by users. This feature allows image system to trace two fast moving objects without using two ROICs. An experimental 64/spl times/64-pixel ROIC has been designed, and it will be fabricated with 0.5/spl mu/m DPTM n-well CMOS process.

A correlated double sample (CDS) stage design is proposed for CMOS image readout IC (ROIC) in this paper. A capacitor transimpedance amplifier (CTIA) stage is used as front stage. A parasitic insensitive switch capacitor (SC) circuit is used to realize CDS on chip. This circuit also supports integration-while-read (IWR) mode, then channels low frequency noise is reduced and frame frequency is increased. A circuit based on this method is fabricated with 1.2 m CMOS technology. The simulation and measurement results are also given in this paper.

A novel readout structure called Forward-Backward-Asynchronous-Reset (FBAR) structure is presented in this paper. This readout structure is used in high performance CMOS readout integrated circuits (ROIC). Using asynchronous reset structure can increase the column OPA's smallest settling time without decreasing frame's readout frequency. By increasing smallest settling time, a low-power column OPA with power dissipation=78 mW can satisfy fast readout speed. While in typical synchronous reset structure, the column OPA's power dissipation may exceed 200 mW to meet readout speed. This improvement can save more than 50% power dissipation of the column readout stage. An experiment ROIC chip using FBAR structure has been fabricated with 1.2 mm DPDM n-well CMOS technology. Testing result shows the total active chip power dissipation is 25 mW.

An improved CMOS snapshot readout structure called RRSCA (Reset Row-by-row Snapshot Charge Amplifier) for infrared focal plane array (IRFPA) is presented in this paper. The pixel circuits in RRSCA readout structure are reset row by row after each row's pixel signals were readout to the column stage in parallel and pixel circuit is very simple including only three MOSFETs. Thus, the RRSCA readout structure is very suitable for the readout circuit design with large-format and very small pixel size such as 30*30 or 25*25 mm2. An experimental 130 t 130 RRSCA chip has been fabricated with 1.2-mm Double-Poly Double-Metal (DPDM) n-well CMOS technology. Both simulation results and experimental results are presented.

This paper details a high performance CMOS linear readout integrated circuit (ROIC) and the measured result. This ROIC realizes time-delay integration (TDI) to enhance the signal to noise ratio (S/N), and defective element deselection (DED) to decrease the probability of bad columns. The Other features include adjustable integration time, multi gain, bi-direction of TDI scan. super-sample, and electrical test. It is fabricated using 1.2-mm double poly double metal (DPDM) CMOS technology. The total power consumption is about 24 mW at 5 V supply voltage.