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Hitting the performance, cost and yield targets for microLED displays that can be used in augmented reality headsets poses formidable challenges. Here we discuss some of those issues and report on the progress of MICLEDI 300mm manufacturing platform. [ABSTRACT FROM AUTHOR]

Electrode grids are used in neuroscience research and clinical practice to record electrical activity from the surface of the brain. However, existing passive electrocorticography (ECoG) technologies are unable to offer both high spatial resolution and wide cortical coverage, while ensuring a compact acquisition system. The electrode count and density are restricted by the fact that each electrode must be individually wired. This work presents an active micro‐electrocorticography (µECoG) implant that tackles this limitation by incorporating metal oxide thin‐film transistors (TFTs) into a flexible electrode array, allowing to address multiple electrodes through a single shared readout line. By combining the array with an incremental‐ΔΣ readout integrated circuit (ROIC), the system is capable of recording from up to 256 electrodes virtually simultaneously, thanks to the implemented 16:1 time‐division multiplexing scheme, offering lower noise levels than existing active µECoG arrays. In vivo validation is demonstrated acutely in mice by recording spontaneous activity and somatosensory evoked potentials over a cortical surface of ≈8×8 mm2. The proposed neural interface overcomes the wiring bottleneck limiting ECoG arrays, holding promise as a powerful tool for improved mapping of the cerebral cortex and as an enabling technology for future brain‐machine interfaces. [ABSTRACT FROM AUTHOR]

In this paper, we discuss microLED display yield and manufacturing challenges related to the CMOS integration as well as epi‐defectivity. Based on those considerations, we show the MICLEDI approach how to address them in a 300mm foundry compatible integration flow. [ABSTRACT FROM AUTHOR]

We have implemented microLED integration into a 300mm CMOS platform with 9150ppi and brightness > 1Mnits. Here we show the impact of light outcoupling optimization on optical crosstalk and efficiency extraction. By implementing wafer level optics we achieve a crosstalk reduction of more than 20dB between neighboring pixels with >20% of the light within the APEX angle of +/‐20deg relevant for waveguide optics. [ABSTRACT FROM AUTHOR]

We show for the first time a microLED display integration flow in a 300mm CMOS manufacturing platform resulting a pixel density of 9150dpi with a 3μm pixel pitch and a brightness for blue μLED in excess of 600kcd/m2 @100A/cm2. [ABSTRACT FROM AUTHOR]

Two different external compensation methods for high‐resolution active matrix organic light‐emitting diode (AMOLED) displays are presented and compared. Both compensation methods are implemented using a small pixel circuit, namely, a 3T2C and a 2T1C pixel circuit, allowing high‐resolution displays. Due to the simple driving schemes, these methods allow fast driving, even for large displays. The characterization results show a significant improvement in current variation by implementing either of these methods. The VT compensation method using a 3T2C pixel circuit is able to reduce the current variation down to 0.56%, whereas the VT‐ and β‐factor compensation method using a 2T1C pixel circuit demonstrates a further reduction in current variations down to 0.079%. This method also clearly shows significant improvement in optical variation between neighboring pixels. [ABSTRACT FROM AUTHOR]

This paper shows the concept and design of a flexible large‐area multi‐fingerprint sensor. The sensor detects the thermal mass of different materials, e.g. the skin with high heat capacity and air with very low heat capacity. We show the device architecture and readout strategies. The performance of the 500ppi flexible sensor is not influenced by bending with a radius of 5mm. [ABSTRACT FROM AUTHOR]

This paper analyzes the effect of high current under illumination stress (HCIS) in self-aligned amorphous indium gallium zinc oxide transistors with Al2O3 as high- $\kappa $ gate dielectric. A negative parallel threshold voltage $({V}_{T}$) shift with the appearance of hysteresis $(\Delta {V}_{{hys}})$ is observed after HCIS. In contrast to the double ionized oxygen vacancy ($\text{V}_{\text O}^{\text 2+}$) theory, a peroxide donor theory based on ${ab~ initio}$ calculations is proposed to explain the degradation. Several methods are carried out to support the mechanism, including $\Delta {V}_{{hys}}$ generation, stress recovery behavior and capacitance-voltage ${(C-V)}$ measurements. A linear dependence between initial ${V}_{T}$ and negative ${V}_{T}$ shift is observed that further supports the peroxide theory. This work highlights the importance of evaluating the HCIS for oxide base semiconductor devices. [ABSTRACT FROM AUTHOR]

In this article, we compare the direct current (dc) and high-frequency performance of two different organic diode structures, a vertical diode and an organic field effect transistor (OTFT) with shorted drain-gate contact, regarding their application in a rectifying circuit. For this purpose, we fabricated both diode structures using the organic semiconductor pentacene. dc measurements were performed showing a space-charge-limited current mobility of more than 0.1 cm2/V s for the vertical diode and a field effect mobility of 0.8 cm2/V s for the OTFT with shorted source-drain. High-frequency measurements of those diode structures in a rectifier configuration show that both types of diodes are able to follow the base-carrier frequency of 13.56 MHz which is essential for viable radio-frequency-identification (rf-ID) tags. Based on those results we evaluate the performance limits and advantages of each diode configuration regarding their application in an organic rf-ID tag. [ABSTRACT FROM AUTHOR]

We present dual‐gate (DG) dual‐layer (a‐ITZO and a‐IGZO) amorphous oxide TFTs integrated on polyimide (PI) foil. The fabricated TFTs show an apparent dual‐gate field‐effect mobility (µFE) of 45.0 cm2/ (V.s), sub‐threshold slope (SS−1) of 0.40 V/decade and ION/IOFF ratio of >108. The DG dual‐layer TFT based ring‐oscillators exhibit faster oscillation frequencies (fosc) compared to DG a‐IGZO TFT based ring‐oscillators. These TFTs are paving the way to faster scan drivers and higher resolution displays. It is also verified that with DG dual‐layer TFTs, the current variation can be reduced when applying an off‐panel compensation method to the asymmetric channel. [ABSTRACT FROM AUTHOR]

This work describes integrated readout electronics for on‐panel fingerprint detection, focusing on two key building blocks: charge sense amplifier (CSA) and analog‐to‐digital converter (ADC). The CSA has been realized in a dual‐gate self‐aligned IGZO thin‐film transistor (TFT) technology with channel length downsizing to 3µm, enabling 1.3mm bezel size for the peripheral readout electronics and 1fps readout of a 1‐Mpixel 500dpi sensor array. The ADC has been realized in two different transistor technologies, IGZO and Indium‐Tin‐Zinc‐Oxide (ITZO). The ITZO ADC achieves a sampling rate of 1kS/s, which is 7.5x faster compared to the IGZO ADC, due to the larger mobility of ITZO. [ABSTRACT FROM AUTHOR]

In this paper, the influence of oxygen partial pressure (${P}_{\textsf {O2}}$) during physical vapor deposition on the field-effect mobility of amorphous InGaZnO (IGZO) thin-film transistor (TFT) is investigated in a wide range of ${P}_{\textsf {O2}}$. The field-effect mobility reduced from 12 to 0.1 cm $^{\textsf {2}}/\textsf {V}~\cdot $ s when the ${P}_{\textsf {O2}}$ is increased from 0.3 to 1.5 mTorr. Temperature-dependent TFT measurements suggest that carrier transport in the TFTs deposited at the ${P}_{\textsf {O2}}$ of 0.3 mTorr can be described according to the multiple trap and release/percolation model. However, the carrier transport in the TFTs deposited at the ${P}_{\textsf {O2}}$ of 1.5 mTorr conforms to Mott’s variable-range hopping model. The elastic recoil detection analysis indicates that hydrogen concentration in the IGZO film increased with ${P}_{\textsf {O2}}$. The X-ray photoelectron spectroscopy results indicate that In vacancy (${V}_{\textsf {In}}$) defects formed in the IGZO film deposited at high ${P}_{\textsf {O2}}$. Scattering induced by hydrogen and pinning of Fermi level below the conduction band edge by ${V}_{\textsf {In}}$ are plausible reasons for the low field-effect mobility in TFTs deposited at high ${P}_{\textsf {O2}}$. [ABSTRACT FROM AUTHOR]

A novel external VT compensation method, using a simple driving scheme, is presented, enabling high resolution, yet uniform displays, regardless of the size. The uniformity can be maintained for initial VT nonuniformities as well as VT shifts occurring during operation, like bias stress. The characterized display area shows a significant reduction in current variation, transforming ~23% variation without compensation into 0.56% variation after calibration. [ABSTRACT FROM AUTHOR]

We present a thin‐film dual‐layer bottom barrier on PI that is compatible with 350°C backplane processing for OLED displays. We demonstrate OLEDs that survive bending over 0.5 mm radius for 10.000x. Furthermore, we show compatibility of the bottom barrier with the backplane process by fabricating AMOLED displays on GEN1‐sized substrates. [ABSTRACT FROM AUTHOR]

We present a 350°C self‐aligned dual‐gate a‐IGZO backplane technology with a monolithically integrated multi‐layer high‐temperature thin‐film barrier for flexible AMOLED. Thin‐film barrier properties and TFT technology are optimized on 320 x 352mm substrates, and demonstrated in a flexible QQVGA 100 ppi AMOLED display prototype. [ABSTRACT FROM AUTHOR]

High resolution RGB OLED frontplane is a key enabler for direct‐view transparent AR displays. 1250 ppi passive displays and semi‐transparent active displays are shown. T90 lifetime at 1000 nit is above 150 hours after patterning. OLED photolithography can provide pixel density above 1000 ppi while keeping high aperture ratio. [ABSTRACT FROM AUTHOR]

Abstract: We present a thin‐film dual‐layer bottom barrier on polyimide that is compatible with 350°C backplane processing for organic light‐emitting diode displays and that can facilitate foldable active‐matrix organic light‐emitting diode devices with a bending radius of <2 mm. We demonstrate organic light‐emitting diodes that survive bending over 0.5 mm radius for 10.000× based on the high‐temperature bottom barrier. Furthermore, we show compatibility of the bottom barrier with the backplane process by fabricating active‐matrix organic light‐emitting diode displays on GEN1‐sized substrates. [ABSTRACT FROM AUTHOR]

Abstract: High‐resolution RGB organic light‐emitting diode frontplane is a key enabler for direct‐view transparent augmented reality displays. In this paper, we demonstrate 1250 ppi passive displays and semi‐transparent active displays. Organic light‐emitting diode photolithography can provide pixel density above 1000 ppi while keeping effective emission area high because of high aperture ratio. Patterns with 2 μm line pitch were successfully transferred to emission layers, indicating possible further pixel density scaling. Lifetime after patterning, key parameter enabling industrialization, is above 150 h (T90 at 1000 nit). [ABSTRACT FROM AUTHOR]

In this work, we have reported dual-gate amorphous indium gallium zinc oxide thin-film transistors (a-IGZO TFTs), where a top-gate self-aligned TFTs has a secondary bottom gate and the TFT integration comprises only five mask steps. The electrical characteristics of a-IGZO TFTs under different gate control are compared. With the enhanced control of the channel with two gates connected together, parameters such as on current (ION), sub-threshold slope (SS−1), output resistance, and bias-stress instabilities are improved in comparison with single-gate control self-aligned a-IGZO TFTs. We have also investigated the applicability of the dual-gate a-IGZO TFTs in logic circuitry such as 19-stage ring oscillators. [ABSTRACT FROM AUTHOR]

We present a qHD (960x540 with 3 sub-pixels) top-emitting AMOLED display with 340ppi resolution using a self-aligned (SA) IGZO TFT backplane on polyimide-foil with humidity barrier. The back plane process flow is based on a 7 layer photolithography process with a CD=4um. We implement a 2T1C pixel engine and use commercial source driver IC made for LTPS. By using IGZO TFT and leveraging the extremely low off-current, we can switch-off the power to the source and gate driver while maintaining the image un-changed for several minutes. We demonstrate that, depending on the image content, low-refresh operation yields reduction in power consumption of up to 50% compared to normal (continuous) operation. We show that with further increase in resolution, the power saving through state retention will be even more significant. [ABSTRACT FROM AUTHOR]

We present a qHD (960 × 540 with three sub-pixels) top-emitting active-matrix organic light-emitting diode display with a 340-ppi resolution using a self-aligned IGZO thin-film transistor backplane on polyimide foil with a humidity barrier. The back plane process flow is based on a seven-layer photolithography process with a CD = 4 μm. We implement a 2T1C pixel engine and use a commercial source driver IC made for low-temperature polycrystalline silicon. By using an IGZO thin-film transistor and leveraging the extremely low off current, we can switch off the power to the source and gate driver while maintaining the image unchanged for several minutes. We demonstrate that, depending on the image content, low-refresh operation yields reduction in power consumption of up to 50% compared with normal (continuous) operation. We show that with the further increase in resolution, the power saving through state retention will be even more significant. [ABSTRACT FROM AUTHOR]

In this study, we have compared the performance of self-aligned a-IGZO thin-film transistors (TFTs) whereby the source/drain (S/D) region's conductivity enhanced in three different ways, that is, using SiNx interlayer plasma (hydrogen diffusion), using calcium (Ca as reducing metal) and using argon plasma (changing the atomic ratio). All these TFTs show comparable characteristics such as field-effect mobility (μFE) of over 10.0 cm²/(V.s), sub-threshold slope (SS-1) of 0.5 V/decade, and current ratio (ION/ IOFF) over 108. However, under negative-bias-illumination-stress (NBIS), all these TFTs showed strong degradation. We attributed this NBIS stability issue to the exposed S/D regions and changes in the conductivity of S/D contact regions. The hydrogen plasma-treated TFTs showed the worst NBIS characteristics. This is linked to increased hydrogen diffusion from the S/D contact regions to the channel. [ABSTRACT FROM AUTHOR]

In this work we present the impact of buffer layers deposited by various techniques such as plasma enhanced chemical deposition (PECVD), physical vapor deposition (PVD) and atomic layer deposition (ALD) techniques on self-aligned (SA) top gate amorphous-Indium-Gallium-Zinc-Oxide (a-IGZO) TFT characteristics. Finally an optimized layer was integrated in TFT backplane on polyimide (PI) foil and a QQVGA AMOLED display is demonstrated. [ABSTRACT FROM AUTHOR]

We present a QVGA (320x240 with 3 sub-pixel) top-emitting AMOLED display with 250ppi resolution using a self-aligned (SA) IGZO TFT backplane on polyimide-foil with full barrier. The back plane process flow is based on a 7 layer photolithography process. The aperture ratio of the top-emitting OLEDs is approx. 80%. An integrated gate driver is shown that can be driven at operation speed equivalent to a 4k2k display at 100Hz. [ABSTRACT FROM AUTHOR]

An integrated scan-line driver, driving half a QQVGA flexible AMOLED display using amorphous-IGZO backplane technology on foil, has been designed and measured. A pulse-width modulation technique has been implemented, enabling to drive the OLEDs with a duty cycle up to almost 100%. The digital driving method also results in a 40% static power reduction of the display. Dynamic logic and bootstrapping techniques enabled the use of clock frequencies up to 300kHz in unipolar amorphous-IGZO technologies on foil. [ABSTRACT FROM PUBLISHER]

The Internet of Things is driving extensive efforts to develop intelligent everyday objects. This requires seamless integration of relatively simple electronics, for example through 'stick-on' electronics labels. We believe the future evolution of this technology will be governed by Wright's Law, which was first proposed in 1936 and states that the cost of a product decreases with cumulative production. This implies that a generic electronic device that can be tailored for application-specific requirements during downstream integration would be a cornerstone in the development of the Internet of Things. We present an 8-bit thin-film microprocessor with a write-once, read-many(WORM)instruction generator that can be programmed after manufacture via inkjet printing. The processor combines organic p-type and soluble oxide n-type thin-film transistors in a new flavor of the familiar complementary transistor technology with the potential to be manufactured on a very thin polyimide film, enabling low-cost flexible electronics. It operates at 6.5 V and reaches clock frequencies up to 2.1 kHz. An instruction set of 16 code lines, each line providing a 9 bit instruction, is defined by means of inkjet printing of conductive silver inks. [ABSTRACT FROM AUTHOR]

In this work, we compared the thin-film transistor (TFT) characteristics of amorphous InGaZnO TFTs with six different source-drain (S/D) metals (MoCr, TiW, Ni, Mo, Al, and Ti/Au) fabricated in bottom-gate bottom-contact (BGBC) and bottom-gate top-contact (BGTC) configurations. In the BGTC configuration, nearly every metal can be injected nicely into the a-IGZO leading to nice TFT characteristics; however, in the BGBC configuration, only Ti/Au is injected nicely and shows comparable TFT characteristics. We attribute this to the metal-containing deposits in the channel and the contact oxidation during a-IGZO layer sputtering in the presence of S/D metal. In bias-stress stability, TFTs with Ti/Au S/D metal showed good results in both configurations; however, in the BGTC configuration, not all the TFTs showed as good bias results as Ti/Au S/D metal TFTs. We attribute this to backchannel interface change, which happened because of the metal-containing deposits at the backchannel during the final the SiO2 passivation. [ABSTRACT FROM AUTHOR]

We present a QQVGA (160times120 with 3 sub-pixel) top-emitting AMOLED display with 85ppi resolution using a self-aligned (SA) IGZO TFT backplane on polyimide-foil. The back plane process flow is based on a 5 layer photolithography process. The aperture ratio of the top-emitting OLEDs is approx. 25%. For operation at 6 V supply voltage (VDD), the brightness of the display exceeds 150cd/m2. On the same substrate a 160 stage gate-driver was measured at FHD rate. [ABSTRACT FROM AUTHOR]

In this work, we report on high-performance bottom-gate top-contact (BGTC) amorphous-Indium-Gallium-Zinc-Oxide (a-IGZO) thin-film transistor (TFT) with SiO2 as an etch-stop-layer (ESL) deposited by medium frequency physical vapor deposition (mf-PVD). The TFTs show field-effect mobility (μFE) of 16.0 cm2/(V.s), sub-threshold slope (SS−1) of 0.23 V/decade and off-currents (IOFF) < 1.0 pA. The TFTs with mf-PVD SiO2 ESL deposited at room temperature were compared with TFTs made with the conventional plasma-enhanced chemical vapor deposition (PECVD) SiO2 ESL deposited at 300 °C and at 200 °C. The TFTs with different ESLs showed a comparable performance regarding μFE, SS−1, and IOFF, however, significant differences were measured in gate bias-stress stability when stressed under a gate field of +/−1 MV/cm for duration of 104 s. The TFTs with mf-PVD SiO2 ESL showed lower threshold-voltage (VTH) shifts compared with TFTs with 300 °C PECVD SiO2 ESL and TFTs with 200 °C PECVD SiO2 ESL. We associate the improved bias-stress stability of the mf-PVD SiO2 ESL TFTs to the low hydrogen content of the mf-PVD SiO2 layer, which has been verified by Rutherford-Back-Scattering-Elastic-Recoil-Detection technique. [ABSTRACT FROM AUTHOR]

We present vertical Schottky diodes based on amorphous IGZO with an unprecedented cutoff frequency of 1.8 GHz at 0 V bias. These diodes have a rectification ratio of up to 10^8 at \pm1~V and a current density of 800 A/cm^2 at +1~V. The diodes' high performance is achieved by understanding and modeling of the two contacts, a Schottky contact using Pd at the bottom and an ohmic contact formed at the top. In particular, the choice of the latter top contact combined with an optimized IGZO layer thickness proves to be crucial: we show how the semiconductor layer thickness and the nature of the top metal modify the doping concentration profile of the IGZO film, which we fully measure and characterize, and how that affects the performance and optimization of the diodes. We measure our diodes in rectifiers, which operate up to 1.1 GHz. Finally, we show that these rectifiers can be fully modeled in SPICE using diode parameters extracted from electrical measurements. [ABSTRACT FROM AUTHOR]

Abstract: In this study, the authors report high‐quality amorphous Indium‐Gallium‐Zinc‐Oxide (a‐IGZO) thin film transistors (TFTs) fabricated using a new back‐channel‐etch (BCE) process flow on Polyethylene Naphthalate (PEN) foil. The BCE flow allows a better scalability of TFTs for high‐resolution backplanes and related circuits. The maximum processing temperature was limited to less than 165oC in order to ensure good overlay accuracy (< 1µm) on foil. The presented process flow differs from to previously reported by defining the Mo S/D contacts by dry etch prior to a‐IGZO patterning. The TFTs show good electrical performance, including field‐effect mobilities in the range of 15.0cm2/(V.s), sub‐threshold slopes of 0.3V/decade and off‐currents <1.0pA on foil. Finally, the applicability of this new BCE process flow was demonstrated for TFT backplane driving a 32 x 32 active‐matrix organic light‐emitting diode (AMOLED) display. [ABSTRACT FROM AUTHOR]

In this study, we report high-quality amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) fabricated on a polyethylene naphthalate foil using a new back-channel-etch (BCE) process flow. The BCE flow allows a better scalability of TFTs for high-resolution backplanes and related circuits. The maximum processing temperature was limited to less than 165 °C in order to ensure good overlay accuracy (<1 µm) on foil. The presented process flow differs from the previously reported flow as we define the Mo source and drain contacts by dry etch prior to a-IGZO patterning. The TFTs show good electrical performance, including field-effect mobilities in the range of 15.0 cm2/(V·s), subthreshold slopes of 0.3 V/decade, and off-currents <1.0 pA on foil. The threshold voltage shifts of the TFTs measured were less than 1.0 V after a stressing time of 104 s in both positive (+1.0 MV/cm) and negative (−1.0 MV/cm) bias directions. The applicability of this new BCE process flow is demonstrated in a 19-stage ring oscillator, demonstrated to operate at a supply voltage of 10 V with a stage delay time of 1.35 µs, and in a TFT backplane driving a 32 × 32 active-matrix organic light-emitting diode display. [ABSTRACT FROM AUTHOR]

We have developed a full color flexible top-emission AMOLED display with 80 ppi resolution using In-Ga-Zn-O TFT backplane on PEN foil under the maximum process temperature of 150 oC. Notwithstanding the low processing temperature, the TFTs with SiOx passivation layer show high reliability with VTH shift of less than 0.2 V at 10,000 seconds under bias-stress of −10 V. [ABSTRACT FROM AUTHOR]

In this study, the authors report on high-quality amorphous indium-gallium-zinc oxide thin-film transistors (TFTs) based on a single-source dual-layer concept processed at temperatures down to 150°C. The dual-layer concept allows the precise control of local charge carrier densities by varying the O2/Ar gas ratio during sputtering for the bottom and top layers. Therefore, extensive annealing steps after the deposition can be avoided. In addition, the dual-layer concept is more robust against variation of the oxygen flow in the deposition chamber. The charge carrier density in the TFT channel is namely adjusted by varying the thickness of the two layers whereby the oxygen concentration during deposition is switched only between no oxygen for the bottom layer and very high concentration for the top layer. The dual-layer TFTs are more stable under bias conditions in comparison with single-layer TFTs processed at low temperatures. Finally, the applicability of this dual-layer concept in logic circuitry such as 19-stage ring oscillators and a TFT backplane on polyethylene naphthalate foil containing a quarter video graphics array active-matrix organic light- emitting diode display demonstrator is proven. [ABSTRACT FROM AUTHOR]

High-performance Schottky diodes based on palladium blocking contacts were fabricated upon depositing indium-gallium-zinc oxide (IGZO) with high oxygen content. We find that an oxygen treatment of the palladium contact is needed to achieve low off currents in the Schottky diode, and rationalize this by relating an increased oxygen content at the Pd/IGZO interface to a lower interfacial trap density. Optimized IGZO films were obtained with a record high ratio of free charge carrier density to subgap traps. The rectification ratios of diodes with such films are higher than 107 with current densities exceeding 103 A/cm2 at low forward bias of 2 V. [ABSTRACT FROM AUTHOR]

The article presents research on n-type metal oxide thin-film transistors (TFTs) in flexible active-matrix organic light-emitting diode (AMOLED) displays. It discusses the performance of solution-based oxide n-type TFTs on low-voltage complementary circuitry on flexible polyimide foil. It explores the significance of the hybrid complementary technology on AMOLED displays.

One of the main drivers for organic electronic research are the backplanes for flexible active-matrix displays using organic light-emitting diodes (AM-OLEDs). In our work, we processed organic thin-film transistors (OTFTs) at low temperatures (<160°C) on poly(ethylene naphthalate) (PEN) foils. There are several challenges in the integration of OLEDs on top of OTFT backplanes on a foil. One of them is the interlayer between the OTFT backplane and the OLEDs. For this layer, low-temperature crosslinkable, chemically resistant polymers are required, which, on the one hand, provide proper electrical insulation to OTFT and OLED devices and, on the other hand, can be processed reliably and provide good adhesion to the OLED anode. From the point of reflectivity and, therefore, light emission efficiency, Ag would be a preferred option. The challenge from the processing point of view is the poor adhesion of evaporated or e-beam deposited Ag on most surfaces. Commonly used microelectronic approaches such as sputtered metal or Ar pre-sputtering cannot be applied because of resulting surface leakage paths on the organic dielectric caused by dangling bonds. To address this issue, we tested a variety of low-temperature crosslinkable polymers (e.g., SU-8, parylene) regarding adhesion, roughness and processability and we measured the adhesion of the Ag deposited at different thicknesses using the Scotch tape test (ASTM D 3359). The best adhesion properties were obtained with parylene N allowing Ag layers with thicknesses up to 200 nm and surface roughness around 7–8 nm. [ABSTRACT FROM AUTHOR]

Parameter variation in organic thin-film transistor (OTFT) technology is known to limit the yield of digital circuits. It is expected that complementary OTFT technology (C-TFT) will reduce the sensitivity to parameter variations. In this paper, we quantify the dependence of yield on transistor parameter variations for C-TFT and compare it to unipolar logic. First, a basic inverter model is developed and fitted to measured transfer characteristics of organic complementary inverters. Next, the inverter model is used in numerical simulations to determine how the noise margin of the inverter, a measure for its reliable operation, changes as a function of transistor parameter variations. The noise margin is significantly improved with respect to p-type-only inverters with similar parameters. Finally, we perform circuit-level yield predictions as a function of parameter spread using the noise-margin simulations performed earlier. [ABSTRACT FROM AUTHOR]