29 results on '"Shamiryan, D."'
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2. Improving mechanical robustness of ultralow-k SiOCH plasma enhanced chemical vapor deposition glasses by controlled porogen decomposition prior to UV-hardening.
3. Growth and characterization of atomic layer deposited WC[sub 0.7]N[sub 0.3] on polymer films.
4. Low dielectric constant materials for microelectronics.
5. Factors affecting an efficient sealing of porous low-k dielectrics by physical vapor deposition Ta(N) thin films.
6. Optimization of low-k UV Curing: Effect of Wavelength on Critical Properties of the Dielectrics.
7. Effect of quartz window temperature on plasma composition during STI etch.
8. Record ION/IOFF performance for 65nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability.
9. Integration challenges for multi-gate devices.
10. Demonstration of recessed SiGe S/D and inserted metal gate on HfO/sub 2/ for high performance pFETs.
11. Demonstration of Ni fully germanosilicide as a pFET gate electrode candidate on HfSiON.
12. Controlling STI-related Parasitic Conduction in 90 nm CMOS and Below.
13. Charging of submicron structures during silicon dioxide etching in one- and two-frequency gas discharges.
14. Effect of energetic ions on plasma damage of porous SiCOH low-k materials.
15. Effects of He Plasma Pretreatment on Low-k Damage during Cu Surface Cleaning with NH3 Plasma.
16. Metrology for Implanted Si Substrate Loss Studies.
17. SELECTIVE REMOVAL OF HIGH-K GATE DIELECTRICS.
18. Plasma etching: From micro- to nanoelectronics.
19. Using Ellipsometry for Assessment of TIN Surface Roughness after Plasma Etch.
20. Influence of crystallographic orientation on dry etch properties of TiN.
21. Diffusion barrier integrity evaluation by ellipsometric porosimetry.
22. Comparative study of SiOCH low-k films with varied porosity interacting with etching and cleaning plasma.
23. Characterization of Cu surface cleaning by hydrogen plasma.
24. Bulk FinFET fabrication with new approaches for oxide topography control using dry removal techniques.
25. Optimization of etching and stripping chemistries for Z3MS/sup TM/ Low-k.
26. Physical and electrical characterization of silsesquioxane-based ultra-low k dielectric films.
27. 8Å Tinv gate-first dual channel technology achieving low-Vt high performance CMOS.
28. Metal Inserted Poly-Si (MIPS) and FUSI dual metal (TaN and NiSi) CMOS integration.
29. 25% drive current improvement for p-type multiple gate FET (MuGFET) devices by the introduction of recessed Si0.8Ge0.2 in the source and drain regions.
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