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Optical second harmonic generation (SHG) can be employed to characterize the passivation quality of semiconducting material interfaces. The interface electric field (EDC) related to the existing charges at and near the interface, including the fixed oxide charges Qox, gives rise to the electric field induced second harmonic phenomenon. In this paper, we calibrate the SHG response for EDC measurement, using Al2O3/SiO2/Si(100) samples with different Qox. To perform this calibration, SHG and capacitance-voltage measurements (to access the electrical field of the samples) were made. The experimental results match well the simulated calibration curve, proving the potential of the SHG as stand-alone characterization technique for dielectric stacks on Si. [ABSTRACT FROM AUTHOR]

Second harmonic generation (SHG) is used to characterize the interfaces of centrosymmetric materials typically used in microelectronic/optoelectronic devices. For such applications, the materials are actually multi-layer stacks, and in this case, the SHG can be difficult to interpret and model. This paper presents the theory of the second harmonic light generated from multilayer structures. The focus is on describing the nonlinear boundary conditions at the interfaces between two different materials, taking into account the distinct contributions of bulk and interface regions. Using these conditions, it is possible to calculate the second harmonic signal from any stack of materials. In this paper, we address stacks containing silicon (100) because it is a material with numerous applications. The nonlinear polarization expressions of the surface and bulk of Si(100), according to Sipe et al. [Phys. Rev. B 35, 1129 (1987)], were integrated into nonlinear boundary conditions in order to determine transmitted and reflected second harmonic waves. An analytical validation was performed on the simple case of an air–silicon interface. For multilayered stacks, the model was compared with experimental results obtained on samples corresponding to pragmatic substrates widely used in microelectronic and optoelectronic applications. [ABSTRACT FROM AUTHOR]

This paper investigates the ability of second harmonic generation (SHG) to probe the passivation quality of atomic layer deposited Al2O3 on Si by estimating the induced interface electric field due to fixed charges in the oxide. Samples with various oxide charges (Qox) and interface state densities (Dit) were fabricated, using different deposition parameters. The samples were characterized by capacitance-voltage (C-V) and microwave photoconductance decay measurements in order to evaluate Qox and Dit, as well as the effective minority carrier lifetime τeff. The SHG results were consistent with Qox, Dit, and τeff values, proving the ability of the technique to monitor the interfacial quality in a contactless and non-destructive way. Optical simulations which use the electric field values obtained from the C-V measurements could reproduce the measured SHG signal. This demonstrates that SHG coupled with optical simulation can give access to the electric field magnitude and thus characterize the electrical properties of oxide/Si interfaces. [ABSTRACT FROM AUTHOR]

This work addresses the origin of the transient body potential variation in silicon on insulator (SOI) with deposited metal contacts, under back-gate bias sweep from accumulation to inversion. The phenomenon arises from the difficulty to inject carriers into the silicon film due to the Schottky contact between the metal and the low p-type doped silicon. The Schottky diode current is controlled by the back-gate voltage, which fixes the potential at the bottom of the low-doped film. When the back-gate voltage drives the silicon film towards inversion, the limited current from the Schottky contact induces a deficit of minority carriers in the film and brings the body potential in an out-of-equilibrium regime. This phenomenon will be reproduced with numerical modelling based on Poisson and continuity equations, including the quasi-Fermi potential. The transient character and its dependence on the Schottky barrier height will be evidenced. A simple and effective combination of the classic Schottky current equation and inversion current calculated from the Lambert function, as in fully depleted (FD)-SOI MOSFETs, confirms the origin of the effect. [ABSTRACT FROM AUTHOR]

This paper presents a detailed investigation of the quasi-static capacitance-voltage (QSCV) technique in pseudo-metal-oxide-semiconductor field effect transistor (pseudo-MOSFET) configuration for evaluating the interface quality of bare silicon-on-insulator (SOI) wafers, without processing dedicated metal-oxide-semiconductor (MOS) test devices. A physical model is developed that is capable of explaining the experimental results. In addition, frequency effects are used to validate the equations by a systematic comparison between experimental and calculated characteristics, as well as by a direct comparison with the standard high-low frequency approach. An extraction procedure for interface trap density based solely on QSCV experimental results is proposed, and limits of the procedure are discussed. The proposed experimental and analytical procedure is demonstrated by characterizing SOI structures with different geometries and with different qualities of surface passivation of the top silicon film. [ABSTRACT FROM AUTHOR]

One of the main issues in the characterization of silicon on insulator (SOI) substrates is to determine the quality of the film-buried oxide interface. This interface quality is strongly connected to the carrier lifetime in the silicon film. In this paper, we extend the well-known pseudo-MOSFET characterization technique for SOI wafers to the extraction of carrier lifetime. The experiment consists in comparing the drain current measured under dark and under laser shining. A model is proposed to evaluate the surface recombination velocity in SOI. Experimental results are validated by numerical simulations. [ABSTRACT FROM AUTHOR]

We extend the pseudo-metal-oxide-semiconductor field-effect transistor (Ψ-MOSFET) technique to the low-temperature range in order to investigate the transport properties of as-fabricated silicon-on-insulator (SOI) wafers. This paper shows experimental results on the temperature dependence of drain current and extracted parameters (hole and electron mobility, subthreshold slope, and threshold voltage). In ultrathin SOI films, the coupling between channel and free surface is strong, degrading the subthreshold swing and threshold voltage. The impact of interface trap density is significant at low temperature. The good correlation between experimental and theoretical curves proves the feasibility of Ψ-MOSFET measurements on bare silicon-on-insulator wafers at low-temperature. [ABSTRACT FROM AUTHOR]

SOI technology offers ample room for scaling, performance improvement, and innovations. The current status is reviewed by focusing on several technological options for boosting the transport properties in SOI MOSFETs. The impact of series resistance, high-K dielectrics, and metal gate in advanced transistors is discussed. Carrier mobility measurements as a function of channel length and temperature reveal the beneficial effect of strain, mitigated however by various types of defects. The experimental data is exclusively collected from state-of-the-art, ultrathin body, fully depleted MOSFETs. Simple models are presented to clarify the mobility behavior. [ABSTRACT FROM AUTHOR]

The feasibility of split C-V measurements for direct evaluation of carrier mobility in as-fabricated silicon-on-insulator wafers has been demonstrated. Here, we complete this letter by modeling the frequency dependence of capacitance curves. The peculiarity of the pseudo-MOSFET (Ψ-MOSFET) configuration with respect to standard MOSFET comes from the possible distribution of mobile carriers beyond the source and drain contacts. This implies a variation in charge spreading and capacitance with frequency that we address with an RC low-pass filter model. Experimental C-V measurements with one and two probes were used for validation of the proposed model. [ABSTRACT FROM AUTHOR]

Pseudo-metal-oxide-semiconductor field-effect transistor (Ψ-MOSFET) is a simple and efficient technique for characterizing electrical properties of silicon-on-insulator wafers. The primary condition for reliable parameter extraction is to achieve ohmic contacts between Ψ-MOSFET probes and silicon film. This paper brings experimental arguments on the probe-pressure impact on contact nature, series resistance, and carrier mobility. The specificity of our study consists of the topographical analysis (by atomic force microscopy) of craters induced by the probes. We correlate the probe-pressure with morphology parameters (size of craters) and electrical parameters (series resistance, mobility). For higher pressures, contacts are improved, changing from Schottky-like to ohmic-like. [ABSTRACT FROM AUTHOR]