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Luminescent radicals are attracting attention as emitters in electroluminescent devices thanks to the exploitation of doublet excitons. Recent studies reveal that exciton formation in radical organic light‐emitting diodes (OLEDs) primarily occurs through a charge trapping mechanism. Although typically detrimental for OLEDs, this might be a key process to elucidate light emission in organic light‐emitting transistors (OLETs). Here, a unipolar n‐type architecture suitable for the implementation of radical emitters is introduced, designed based on computational calculations. The operation of the as‐realized devices incorporating the newly synthesized [2,6‐dichloro‐4‐(2,6‐dimethoxyphenyl)phenyl](3,5‐dichloro‐4‐pyridyl) (2,4,6‐trichlorophenyl)methyl radical is investigated via transient electroluminescence measurements to demonstrate the occurrence of long‐living emission ascribed to the charge trapping mechanisms. Moreover, a comprehensive understanding of the processes governing radical‐OLET is obtained by recording complete 2D maps of both optical and electrical response of the device as a function of applied voltages. Notably, the trapping of electrons by radical moieties is demonstrated to generate a negative charge density in the emissive layer that facilitates holes to be injected: increasing the balance of opposite charge carriers, a tenfold enhancement of the external quantum efficiency (EQE) at the proper source‐drain and source‐gate voltage conditions is reported to reach a maximum EQE value of 0.2%. [ABSTRACT FROM AUTHOR]

Dielectric capacitors are widely used in aerospace, power systems, and other fields. Working environments with ever‐increasing temperatures pose a new challenge to energy storage performance. Polyetherimide (PEI) has gained extensive research for its good high‐temperature properties. In order to further improve its energy storage performance at high temperatures, many researchers have worked on PEI all‐organic composites doping with molecular semiconductors. Previous studies generally only considered the effect of introduced deep traps on macroscopic properties such as electrical conductivity, electrical breakdown, and energy storage performance. It has been shown that only qualitative analyses can be performed from the perspective of charge trapping, and it is difficult to obtain quantitative results. Therefore, this work proposes to study the macroscopic properties of polymer dielectrics by combining charge trapping with molecular displacement. A comprehensive conduction‐breakdown‐energy storage model was established to explain the influence mechanism of molecular semiconductors on the improved energy storage performance of PEI composites at high temperatures. The molecular semiconductor fillers increase the coefficient of friction between molecular chains, which restricts the movement of molecular chains and also limits charge hopping. Therefore, the dielectrics have higher breakdown strengths and smaller conduction losses, which synergistically enhance the energy storage performance. [ABSTRACT FROM AUTHOR]

This work investigates the gate oxide reliability of commercial 1.2 kV silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) with planar and trench gate structures. The performance of threshold voltage (V t h) and gate leakage current (I g s s) in SiC MOSFETs is evaluated under positive and negative gate voltage stress. The oxide lifetimes of SiC planar and trench MOSFETs at 150 °C are measured using constant voltage Time-Dependent Dielectric Breakdown (TDDB) testing. From the test results, it is found that electron trapping and hole trapping in S i O 2 caused by oxide electric field (E o x)  stress affect the V t h of SiC MOSFETs. The saturation and turnaround behavior of the V t h shift during positive and negative gate voltage stresses indicates that the influence of charge trapping in the gate oxide varies with stress time. The I g s s under positive and negative gate voltages depends on the tunneling barrier height for electrons and holes, respectively, which can be calculated using the Fowler–Nordheim (FN) tunneling mechanism. Moreover, the presence of near-interface traps (NITs) affects the barrier height for holes under negative gate voltages. The behavior of V t h shift and I g s s under high-temperature gate bias reflects the charge trapping occurring in different regions of the gate oxide. In addition, compared to SiC planar MOSFETs, SiC trench MOSFETs with thicker gate oxide tend to exhibit higher lifetimes in TDDB tests. [ABSTRACT FROM AUTHOR]

Triboelectric nanogenerators (TENGs) have become reliable green energy harvesters by converting biomechanical motions into electricity. However, the inevitable charge leakage and poor electric field (EF) of conventional TENG result in inferior tribo‐charge density on the active layer. In this paper, TiO2‐MXene incorporated polystyrene (PS) nanofiber membrane (PTMx NFM) charge trapping interlayer is introduced into single electrode mode TENG (S‐TENG) to prevent electron loss at the electrode interface. Surprisingly, this charge‐trapping mechanism augments the surface charge density and electric output performance of TENGs. Polyvinylidene difluoride (PVDF) mixed polyurethane (PU) NFM is used as tribo‐active layer, which improves the crystallinity and mechanical property of PVDF to prevent delamination during long cycle tests. Herein, the effect of this double‐layer capacitive model is explained experimentally and theoretically. With optimization of the PTMx interlayer thickness, S‐TENG exhibits a maximum open‐circuit voltage of (280 V), short‐circuit current of (20 µA) transfer charge of (120 nC), and power density of (25.2 µW cm−2). Then, this energy is utilized to charge electrical appliances. In addition, the influence of AC/DC EF simulation in wound healing management (vitro L929 cell migration, vivo tissue regeneration) is also investigated by changing the polarity of trans‐epithelial potential (TEP) distribution in the wounded area. [ABSTRACT FROM AUTHOR]

The charge carrier mobility in tris(4‐carbazoyl‐9‐ylphenyl)amine (TCTA), a host and hole transport material typically used in organic light‐emitting diodes (OLEDs), is measured using charge carrier electrical injection metal–insulator–semiconductor charge extraction by linearly increasing voltage (i‐MIS‐CELIV). By employing the injection current i‐MIS‐CELIV method, charge transport at time scales shorter than the transit times typically observed in standard MIS‐CELIV is measured. The i‐MIS‐CELIV technique enables the experimental measurement of unequilibrated and pretrapped charge carriers. Through a comparison of injection and extraction current transients obtained from i‐MIS‐CELIV and MIS‐CELIV, it is concluded that hole trapping is negligible in evaporated neat films of TCTA within the time‐scales relevant to the operational conditions of optoelectronic devices, such as OLEDs. Furthermore, photocarrier generation in conjunction with i‐MIS‐CELIV (photo‐i‐MIS‐CELIV) to quantify the properties of charge injection from the electrode to the semiconductor of the MIS devices is utilized. Based on the photo‐i‐MIS‐CELIV measurements, it is observed that the contact resistance does not limit the injection current at the TCTA/molybdenum oxide/silver interface. Therefore, when TCTA is employed as the hole transport/electron‐blocking layer in OLEDs, it does not significantly reduce the injection current and remains compatible with the high injection current densities required for efficient OLED operation. [ABSTRACT FROM AUTHOR]

This study demonstrates a significant enhancement in the performance of thin-film transistors (TFTs) in terms of stability and mobility by combining indium–tungsten oxide (IWO) and zinc oxide (ZnO). IWO/ZnO heterojunction structures were fabricated with different channel thickness ratios and annealing environments. The IWO (5 nm)/ZnO (45 nm) TFT, annealed in O2 ambient, exhibited a high mobility of 26.28 cm2/V·s and a maximum drain current of 1.54 μA at a drain voltage of 10 V, outperforming the single-channel ZnO TFT, with values of 3.8 cm2/V·s and 28.08 nA. This mobility enhancement is attributed to the formation of potential wells at the IWO/ZnO junction, resulting in charge accumulation and improved percolation conduction. The engineered heterojunction channel demonstrated superior stability under positive and negative gate bias stresses compared to the single ZnO channel. The analysis of O 1s spectra showed OI, OII, and OIII peaks, confirming the theoretical mechanism. A bias temperature stress test revealed superior charge-trapping time characteristics at temperatures of 25, 55, and 85 °C compared with the single ZnO channel. The proposed IWO/ZnO heterojunction channel overcomes the limitations of the single ZnO channel and presents an attractive approach for developing TFT-based devices having excellent stability and enhanced mobility. [ABSTRACT FROM AUTHOR]

Phototransistor using 2D semiconductor as the channel material has shown promising potential for high sensitivity photo detection. The high photoresponsivity is often attributed to the photogating effect, where photo excited holes are trapped at the gate dielectric interface that provides additional gate electric field to enhance channel charge carrier density. Gate dielectric material and its deposition processing conditions can have great effect on the interface states. Here, we use HfO2 gate dielectric with proper thermal annealing to demonstrate a high photoresponsivity MoS2 phototransistor. When HfO2 is annealed in H2 atmosphere, the photoresponsivity is enhanced by an order of magnitude as compared with that of a phototransistor using HfO2 without annealing or annealed in Ar atmosphere. The enhancement is attributed to the hole trapping states introduced at HfO2 interface through H2 annealing process, which greatly enhances photogating effect. The phototransistor exhibits a very large photoresponsivity of 1.1 × 107 A W−1 and photogain of 3.3 × 107 under low light illumination intensity. This study provides a processing technique to fabricate highly sensitive phototransistor for low optical power detection. [ABSTRACT FROM AUTHOR]

For operation as power amplifiers in RF applications, high electron mobility transistor (HEMT) structures are subjected to a range of bias conditions, applied at both the gate and drain terminals, as the device is biased from the OFF- to ON-state conditions. The stability of the device threshold voltage (Vt) condition is imperative from a circuit-design perspective and is the focus of this study, where stresses in both the ON and OFF states are explored. We see rapid positive threshold voltage increases under negative bias stress and subsequent recovery (i.e., Vt reduces), whereas conversely, we see a negative Vt shift under positive stress and Vt increase during the subsequent relaxation phase. These effects are correlated with the thickness of the GaN layer and ultimately result from the deep carbon-acceptor levels in the C-GaN back barrier incorporated to screen the buffer between the silicon substrate and the epitaxially grown GaN layer. Methods to mitigate this effect are explored, and the consequences are discussed. [ABSTRACT FROM AUTHOR]

Photocatalytic hydrogen evolution (PHE) from water splitting is a promising technology for clean and renewable energy production. Elemental crystalline red phosphorus (CRP) is purposefully designed and developed for PHE reaction. However, the photocatalytic activity of CRP is limited by its intrinsic P vacancy (VP) defects, which lead to detrimental charge trapping at deep states and hence its severe recombination. To address this issue, a boron (B) incorporated CRP (B‐CRP) photocatalyst is tailored, synthesized via a simple and mild boric acid‐assisted hydrothermal strategy. The incorporation of B effectively fills the VP defects, reducing deep trap states (DTS) and introducing beneficial shallow trap states (STS) within the band structure of CRP. This defect engineering approach leads to enhanced photocatalytic activity, with B‐CRP achieving a PHE rate of 1392 µmol g−1 h−1, significantly outperforming most reported elemental photocatalysts in the literature. Density functional theory (DFT) simulations and ultrafast spectroscopy support the constructive role of B‐dopant‐induced STS in prolonging active charge carrier lifetimes, promoting more efficient photocatalytic reactions. The findings not only demonstrate the effectiveness of B‐CRP as a photocatalyst but also highlight the usefulness of dopant‐induced STS in advancing PHE technologies. [ABSTRACT FROM AUTHOR]

Artificial synaptic devices (ASDs) are attracting widespread attention as highly promising components for use in complex neuromorphic systems, playing crucial roles in addressing the challenges posed by the conventional von Neumann architecture. However, the instabilities of ASDs in high‐temperature environments diminish the reliabilities of the device performances, significantly inhibiting their practical application. Herein, a highly reliable 2D MoS2/GaPS4 ASD that maintains its functionality even after exposure to 400 °C is proposed. Moreover, due to the enhanced charge‐trapping effect of the GaPS4 layer, the memory window expands from an initial 42 to 55 V, accompanied by a substantial on/off ratio of 105, low off‐leakage current of 10−11 A, and high number of endurance cycles (103). The device effectively simulates various biological synaptic functions via electric and light stimulation. Notably, the high electric and light paired‐pulse facilitation indices suggest an exceptional synaptic performance. The findings introduce a novel approach to high‐temperature neuromorphic applications via defect engineering. [ABSTRACT FROM AUTHOR]

Crystalline calcium fluoride (CaF2) is drawing significant attention due to its great potential of being the gate dielectric of two-dimensional (2D) material MOSFETs. It is deemed to be superior to boron nitride and traditional silicon dioxide (SiO2) because of its larger dielectric constant, wider band gap, and lower defect density. Nevertheless, the CaF2-based MOSFETs fabricated in the experiment still present notable reliability issues, and the underlying reason remains unclear. Here, we studied the various intrinsic defects and adsorbates in CaF2/molybdenum disulfide (MoS2) and CaF2/molybdenum disilicon tetranitride (MoSi2N4) interface systems to reveal the most active charge-trapping centers in CaF2-based 2D material MOSFETs. An elaborate Table comparing the importance of different defects in both n-type and p-type devices is provided. Most impressively, the oxygen molecules (O2) adsorbed at the interface or surface, which are inevitable in experiments, are as active as the intrinsic defects in channel materials, and they can even change the MoSi2N4 to p-type spontaneously. These results mean that it is necessary to develop a high-vacuum packaging process, as well as prepare high-quality 2D materials for better device performance. [ABSTRACT FROM AUTHOR]

Photostimulated luminescence phosphors are promising candidates for next‐generation optical data storage devices. Herein, optically‐reversible luminescence modulation is demonstrated using UV wavelengths in the fluoroperovskite RbCdF3:Mn, where the modulation is mediated by photostimulated luminescence processes. UV‐C stimulation enhances the luminescence from Mn2+ centers and simultaneously fills electron traps. This charging process occurs via electron transfer from Mn2+ ions to fluorine vacancies, yielding Mn3+ ions and F‐centers, and is mediated by conduction band transport. UV‐A stimulation restores the material to the initial state. This discharging process occurs via electron transfer from F‐centers to Mn3+ ions and is similarly mediated by conduction band transport. Moreover, the discharging process manifests Mn2+ photostimulated luminescence. The primary trap state has activation energies in the range 1.46 to 1.73 eV and has room temperature lifetimes exceeding 40 000 years. A kinetic model is presented and evaluated that accurately describes the charge transport and luminescence properties of the material. Thus, a material is presented via which ultra‐long term, multi‐level luminescent data storage can be realized, and a model via which precise control over the luminescence modulation and photostimulated luminescence intensities can be achieved. [ABSTRACT FROM AUTHOR]

Neuromorphic devices, which can mimic the human body's neural system, are rising as an essential technology for artificial intelligence. Here, two types of organic synaptic transistors (OSTRs), OSTR‐A and OSTR‐B, are fabricated on either glass or polymer film using water‐processable charge‐trapping gate‐insulating layers that are prepared by reacting ethylenediamine (EDA) and poly(2‐acrylamido‐2‐methyl‐1‐propanesulfonic acid) (PAMPSA). OSTR‐A is designed to function as a basic artificial synapse by gate pulse stimulation only, while OSTR‐B has additional near‐infrared (NIR)‐absorbing conjugated polymer layers for further sensing of NIR light upon gate voltage stimulations. The PAMPSA:EDA films are found to contain permanent charge bridges (ion pairs of –SO3− +NH3‐) that play a charge‐trapping role in OSTRs. Both devices with the PAMPSA:EDA layers exhibit clear postsynaptic current (PSC) signals upon gate voltage pulses, leading to long‐term potentiation/depression characteristics. The flexible OSTR‐B devices can sense the NIR light (905 nm) upon gate pulse stimulation and their PSC signals are well maintained even after bending (>5000 times). Artificial neural network simulations disclose that the flexible OSTR‐B devices can stably perform synaptic operations under the NIR light with high accuracy (>90%) even after repeated bending (5000 times), indicative of potential use in artificial neuromorphic skin applications. [ABSTRACT FROM AUTHOR]

Although 2D material van der Waals heterostructures (vdWHs) exhibit many novel properties and applications, 2D homojunctions have unique advantages in interface lattice matching, band continuity, and charge transfer efficiency. However, the rectification performances of 2D homojunction diodes are severely limited by the small junction barrier, mainly due to inefficient charge doping. In this work, an ultrahigh‐rectification‐ratio WSe2 homojunction diode achieved by the semi‐floating gate doping of graphdiyne oxide (GDYO) is reported. Utilizing the WSe2/GDYO direct charge trapping mode can free the inhibition of charge capturing efficiency by removing conventional insulating barriers and thus improve the rectification ratio. The C─C(sp) and oxygen‐containing functional groups in the GDYO layer can provide outstanding charge‐trapping ability due to their unsaturation. Furthermore, the oxygen plasma treatment used for oxidizing graphdiyne (GDY) into GDYO can make GDYO a flatter surface, thus creating strong‐coupling WSe2/GDYO interfaces to improve the charge transfer efficiency and enhance the electrostatic doping effect. Besides, the WSe2/GDYO interfaces are confirmed to possess a higher junction barrier than that of the WSe2/GDY interfaces. This research proposes a brand‐new approach to building p–n junctions via charge trapping and the homojunction diode with a record‐highest rectification ratio of up to 106 is obtained. [ABSTRACT FROM AUTHOR]

Nonvolatile memory is an indispensable component of electronic devices. However, the current technology makes it difficult to satisfy the emerging big data demand. To circumvent the existing problems, herein, a first attempt is made to achieve multifunctional nonvolatile memory based on all 2D heterostructures, consisting of histidine‐doped molybdenum disulfide quantum disks mixed with graphene oxide and a graphene macroscopic heterojunction. The designed device possesses intriguing hybrid electrically and optically controllable nonvolatile memory functionalities. By harnessing the unique properties of these materials, memory devices demonstrate long‐term stability and nonvolatile characteristics under both optical and electrical control signals. These devices possess outstanding features, such as multiple read‐write cycles, multi levels, and fast switching speeds, overcoming the limitations of traditional components. To explore the underlying physical mechanism, the Fermi level of graphene is measured and it is confirmed that the charge transfer and trapping across the heterojunctions are the major factors responsible for the observed behavior. This study demonstrates that 2D heterostructures for hybrid optically and electrically controllable nonvolatile memory pave an alternative route for the next‐generation information technology. [ABSTRACT FROM AUTHOR]

The majority of voltage-gated ion channels contain a defined voltage-sensing domain and a pore domain composed of highly conserved amino acid residues that confer electrical excitability via electromechanical coupling. In this sense, the voltage-gated proton channel (Hv1) is a unique protein in that voltage-sensing, proton permeation and pH-dependent modulation involve the same structural region. In fact, these processes synergistically work in concert, and it is difficult to separate them. To investigate the process of Hv1 voltage sensor trapping, we follow voltage-sensor movements directly by leveraging mutations that enable the measurement of Hv1 channel gating currents. We uncover that the process of voltage sensor displacement is due to two driving forces. The first reveals that mutations in the selectivity filter (D160) located in the S1 transmembrane interact with the voltage sensor. More hydrophobic amino acids increase the energy barrier for voltage sensor activation. On the other hand, the effect of positive charges near position 264 promotes the formation of salt bridges between the arginines of the voltage sensor domain, achieving a stable conformation over time. Our results suggest that the activation of the Hv1 voltage sensor is governed by electrostatic–hydrophobic interactions, and S4 arginines, N264 and selectivity filter (D160) are essential in the Ciona-Hv1 to understand the trapping of the voltage sensor. [ABSTRACT FROM AUTHOR]

This study focuses on InGaZnO-based synaptic devices fabricated using reactive radiofrequency sputtering deposition with highly uniform and reliable multilevel memory states. Electron trapping and trap generation behaviors were examined based on current compliance adjustments and constant voltage stressing on the ITO/InGaZnO/ITO memristor. Using O2 + N2 plasma treatment resulted in stable and consistent cycle-to-cycle memory switching with an average memory window of ~95.3. Multilevel resistance states ranging from 0.68 to 140.7 kΩ were achieved by controlling the VRESET within the range of −1.4 to −1.8 V. The modulation of synaptic weight for short-term plasticity was simulated by applying voltage pulses with increasing amplitudes after the formation of a weak conductive filament. To emulate several synaptic behaviors in InGaZnO-based memristors, variations in the pulse interval were used for paired-pulse facilitation and pulse frequency-dependent spike rate-dependent plasticity. Long-term potentiation and depression are also observed after strong conductive filaments form at higher current compliance in the switching layer. Hence, the ITO/InGaZnO/ITO memristor holds promise for high-performance synaptic device applications. [ABSTRACT FROM AUTHOR]

Two-dimensional rhenium disulfide (ReS2), a member of the transition-metal dichalcogenide family, has received significant attention due to its potential applications in field-effect transistors (FETs), photodetectors, and memories. In this work, we investigate the suppression of the subthreshold current during the forward voltage gate sweep, leading to an inversion of the hysteresis in the transfer characteristics of ReS2 nanosheet-based FETs from clockwise to anticlockwise. We explore the impact of temperature, sweeping gate voltage, and pressure on this behavior. Notably, the suppression in current within the subthreshold region coincides with a peak in gate current, which increases beyond a specific temperature but remains unaffected by pressure. We attribute both the suppression in drain current and the presence of peak in gate current to the charge/discharge process of gate oxide traps by thermal-assisted tunnelling. The suppression of the subthreshold current at high temperatures not only reduces power consumption but also extends the operational temperature range of ReS2 nanosheet-based FETs. [ABSTRACT FROM AUTHOR]

This study investigates the electrical characteristics observed in n-channel and p-channel ferroelectric field effect transistor (FeFET) devices fabricated through a similar process flow with 10 nm of ferroelectric hafnium zirconium oxide (HZO) as the gate dielectric. The n-FeFETs demonstrate a faster complete polarization switching compared to the p-channel counterparts. Detailed and systematic investigations using TCAD simulations reveal the role of fixed charges and interface traps at the HZO-interfacial layer (HZO/IL) interface in modulating the subthreshold characteristics of the devices. A characteristic crossover point observed in the transfer characteristics of n-channel devices is attributed with the temporary switching between ferroelectric-based operation to charge-based operation, caused by the pinning effect due to the presence of different traps. This experimental study helps understand the role of charge trapping effects in switching characteristics of n- and p-channel ferroelectric FETs. [ABSTRACT FROM AUTHOR]

Pseudo-ferroelectric transistors have attracted particular interest owing to their applications in the non-volatile memories and neuromorphic circuits; however, it remains to be explored in the limit of few-layer devices. Here we reveal a pseudo-ferroelectric phenomenon in the ultrathin graphene/black phosphorene (G/BP) heterostructure by first-principles calculations. Putting forward an excitation-assisted mechanism, the ferroelectric-like hysteresis loop can be explained by a combined effect of the external electric fields dependent bipolarity and anisotropy in the G/BP heterostructure. Considering the build-in electric field, the bipolar behavior results in the multistate effect of the G/BP heterostructure when modulating the applied electric field. The anisotropic hybridization caused by the susceptible Dirac electrons in graphene and the large in-plane anisotropy in BP provides the interfacial states, which trap excitations and stabilize the multistate. The pseudo-ferroelectric behavior should be useful for interpreting transport experiments in gated G/BP devices and exploring its applications in memories or synaptic devices. [ABSTRACT FROM AUTHOR]

Artificial synapses are key elements in building bioinspired, neuromorphic computing systems. Ferroelectric field‐effect transistors (FeFETs) with excellent controllability and complementary metal oxide semiconductor (CMOS) compatibility are favorable to achieving synaptic functions with low power consumption and high scalability. However, because of the only nonvolatile ferroelectric (Fe) characteristics in the FeFET, it is difficult to develop bioplausible short‐term synaptic elements for spatiotemporal information processing. By judiciously combining defects (DE) and Fe domains in gate stacks, a compact artificial synapse featuring spatiotemporal information processing on a single Fe–DE fin FET (FinFET) is proposed. The devices are designed to work in a separate DE mode to induce short‐term plasticity by spontaneous charge detrapping, and a hybrid Fe–DE mode to trigger long‐term plasticity through the coupling of defects and Fe domains. The capability of the compact synapse is demonstrated by differentiating 16 temporal inputs. Moreover, the highly controllable static electricity of advanced FinFETs leads to an ultralow power of 2 fJ spike−1. An all Fe–DE FinFET reservoir computing (RC) system is then constructed that achieves a recognition accuracy of 97.53% in digit classification. This work enables constructing RC systems with fully advanced CMOS‐compatible devices featuring highly energy‐efficient and low‐hardware systems. [ABSTRACT FROM AUTHOR]

To further improve the output performance of triboelectric devices, reducing charge attenuation and loss has become a hot research topic. Particularly, textiles have emerged as one of the promising research directions for triboelectric devices owing to their special internal structure and large specific surface area. In the present work, polyacrylonitrile fibers are fabricated with two distinct structures to provide a higher dielectric constant due to the strong polar properties brought about by higher dipole moment of the CN group. In addition, the complex and closely connected structure of the textile increases specific internal surface area. As a friction layer, the output voltage is shown to increase to 625% of the initial value (from 8 to 60 V) after the application of friction for a short time due to accumulation property. When acting as a trapping layer, the charge loss after injection is effectively prevented due to excellent charge trapping effect. After 24 h, the triboelectric output performance remains at ≈70% of the initial value (decreasing from 320 to 220 V), which is more than 20 times that of the polytetrafluoroethylene film, which decreases from 125 to 19 V. The device is realized for the advanced application of multi‐modal sensors. [ABSTRACT FROM AUTHOR]

Sufficient energy consumption for conventional information processing makes it necessary to look for new computational methods. One of the possible solutions to this problem is neuromorphic computations using memristive devices. Memristors based on molybdenum disulfide (MoS2$\left(\text{MoS}\right)_{2}$) are a promising way to provide a sizeable amount of hysteresis at low energy costs. Herein, different configurations of MoS2$\left(\text{MoS}\right)_{2}$ memristors as well as the mechanisms involved in hysteresis formation are shown. Bottom gated configuration is beneficial in terms of hysteresis area and energy efficiency. The impact of device channel dimensions on the hysteresis area and energy consumption is discussed. Different operation conditions with triangular, rectangular, sinusoidal, and sawtooth drain‐to‐source pulses are simulated, and rectangular pulses demonstrate the highest energy efficiency. The study shows the potential to realize low‐power neuromorphic systems using MoS2$\left(\text{MoS}\right)_{2}$ memristive devices. [ABSTRACT FROM AUTHOR]

To avoid the complexity of the circuit for in‐memory computing, simultaneous execution of multiple logic gates (OR, AND, NOR, and NAND) and memory behavior are demonstrated in a single device of oxygen plasma‐treated gallium selenide (GaSe) memtransistor. Resistive switching behavior with RON/ROFF ratio in the range of 104 to 106 is obtained depending on the channel length (150 to 1600 nm). Oxygen plasma treatment on GaSe film created shallow and deep‐level defect states, which exhibit carriers trapping/de‐trapping, that lead to negative and positive photoconductance at positive and negative gate voltages, respectively. This distinguishing feature of gate‐dependent transition of negative to positive photoconductance encourages the execution of four logic gates in the single memory device, which is elusive in conventional memtransistor. Additionally, it is feasible to reversibly switch between two logic gates by just adjusting the gate voltages, e.g., NAND/NOR and AND/NAND. All logic gates presented high stability. Additionally, memtransistor array (1×8) is fabricated and programmed into binary bits representing ASCII (American Standard Code for Information Interchange) code for the uppercase letter "N". This facile device configuration can provide the functionality of both logic and memory devices for emerging neuromorphic computing. [ABSTRACT FROM AUTHOR]

Amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) have attracted much attention owing to their promising applications, such as display devices and dynamic random access memory (DRAM) devices. This study reports a comprehensive study on the bias temperature instability of a-IGZO TFTs. We analyzed the behavior of transfer characteristics, under repeated bias stress and recovery at different temperatures, to unveil the degradation mechanism of bias and thermal stress. Based on threshold voltage, subthreshold swing, and field-effect mobility, the correlation between transfer characteristics and stress time was found to depend on temperature, revealing the opposite trends. The trends are interpreted using two mechanisms: trapped electron and oxygen vacancy. The consequential behavior of transfer characteristics under repeated stress and recovery depended on the competition between the two mechanisms, and the result of the competition depended on the temperature. The predominant mechanism was determined based on the temperature, and a high temperature enhanced the generation of oxygen vacancies, resulting in a negative shift at high temperatures. Repeated stress revealed that the predominant mechanisms were maintained with constant VT shifts over cycles, and repeated recovery confirmed the difference in recovery mechanisms with increasing VT shifts over cycles. Understanding the competition between the two main mechanisms aids in explaining the bias temperature instability of a-IGZO TFTs. [ABSTRACT FROM AUTHOR]

Rather than generating a photocurrent through photo-excited carriers by the photoelectric effect, the photogating effect enables us to detect sub-bandgap rays. The photogating effect is caused by trapped photo-induced charges that modulate the potential energy of the semiconductor/dielectric interface, where these trapped charges contribute an additional electrical gating-field, resulting in a shift in the threshold voltage. This approach clearly separates the drain current in dark versus bright exposures. In this review, we discuss the photogating effect-driven photodetectors with respect to emerging optoelectrical materials, device structures, and mechanisms. Representative examples that reported the photogating effect-based sub-bandgap photodetection are revisited. Furthermore, emerging applications using these photogating effects are highlighted. The potential and challenging aspects of next-generation photodetector devices are presented with an emphasis on the photogating effect. [ABSTRACT FROM AUTHOR]

Gray scale consistency in pixels was extremely important for electrowetting displays (EWDs). However, traditional electrowetting display driving waveforms could not obtain a pixel aperture ratio consistency, which led to the occurrence of gray inconsistency even if it was the same driving waveform. In addition, the oil backflow caused by charge trapping could not be sustained. Therefore, a multi-direct current (DC) overdriving waveform for gray scale consistency was proposed in this paper, which could effectively improve the performance of EWDs. The driving waveform was divided into a start-up driving phase and a stable driving phase. The stable driving phase was composed of a square wave with a duty cycle of 79% and a frequency of 43 Hz. Subsequently, an overdriving pulse was also introduced in the stable driving phase. The multi-DC driving waveform for gray scale consistency was applied to a thin film transistor-electrowetting display (TFT-EWD). The average difference between increasing driving voltage and decreasing driving voltage was only 2.79%. The proposed driving waveform has an aperture ratio of 3.7 times at low voltages compared to DC driving. [ABSTRACT FROM AUTHOR]

A full understanding of the impact of charge trapping on the memory window (MW) of HfO2-based ferroelectric field effect transistors (FeFETs) will permit the design of program and erase protocols, which will guide the application of these devices and maximize their useful life. The effects of charge trapping have been studied by changing the parameters of the applied program and erase pulses in a test sequence. With increasing the pulse amplitude and pulse width, the MW increases first and then decreases, a result attributed to the competition between charge trapping (CT) and ferroelectric switching (FS). This interaction between CT and FS is analyzed in detail using a single-pulse technique. In addition, the experimental data show that the conductance modulation characteristics are affected by the CT in the analog synaptic behavior of the FeFET. Finally, a theoretical investigation is performed in Sentaurus TCAD, providing a plausible explanation of the CT effect on the memory characteristics of the FeFET. This work is helpful to the study of the endurance fatigue process caused by the CT effect and to optimizing the analog synaptic behavior of the FeFET. [ABSTRACT FROM AUTHOR]

Developing memristor with photosensing behavior would facilitate the construction of an advanced neuromorphic computing framework for future sensing−memory−computing integrated system. Although the memristor has already got much attention, its optoelectronic sensing mechanism is still unclear, thus the enhancement is challenging. Herein, a MoS2 memristor is fabricated on the oxygen‐vacancy‐rich Bi1.5MgNb1.5O7 thin film. By combining the voltage stress and photoexcitation, the memristor, its photosensing property, and their correlation have been systematically studied. The results show that the interfacial oxygen vacancy can trap the photogenerated electron obeying the photogating effect which tunes the Fermi level of MoS2 and exhibits tunable hysteresis behavior. The photoexcitation mechanism has been studied showing wavelength and voltage‐dependent photosensing−memory performance. The responsivity can reach up to 2 × 1011 V W−1 at 550 nm illumination and the hysteresis ratio (ΔH/Vg), one of the factors determining the memory, can be modulated by 40 times, which is larger than for previous 2D materials‐based memristors. Contour maps of external quantum efficiency show illumination, voltage, and wavelength dependence where the value becomes larger at lower illumination power density and higher voltage. This study reveals the interfacial enhanced photosensing mechanism of MoS2 device and provides new way to enrich memristor performance. [ABSTRACT FROM AUTHOR]

Field-effect transistors based on organic semiconducting materials (OFETs) have unique advantages of intrinsically mechanical flexibility, simple preparation process, low manufacturing cost, and large-area preparation. Through the innovation of new material design and device structures, the performance of device parameters such as mobility, on–off current ratio, and the threshold voltage (VTH) of OFETs continues to improve. However, the VTH shift of OFETs has always been an important problem restricting their practical applications. In this work, we observe that the VTH of polymer OFETs with the widely investigated device structure of a SiO2 bottom-gate dielectric is noticeably shifted by pre-applying a large gate voltage. Such a shift in VTH remains to a large extent, even after modifying the surface of the SiO2 dielectric using a hexamethyldisilazane (HMDS) self-assembled monolayer. This behavior of VTH can be ascribed to the charge trappings at the bulk of the SiO2. In addition, the generality of this observation is further proven by using two other conjugated polymers including p-type PDPP3T and n-type PTzNDI-2FT, and a similar trend is obtained. [ABSTRACT FROM AUTHOR]

Ferroelectric field-effect transistors (FeFETs) have become an attractive technology for memory and emerging applications on a silicon electronic platform after the discovery of the ferroelectric phase in silicon-friendly hafnium oxide insulators. In this tutorial, we review one nonideal physical phenomenon that determines the device operation of practical FeFETs based on ferroelectric hafnium oxide (FE-HfO2) insulators and silicon channels: polarization-induced electron trapping. The ferroelectric polarization in FE-HfO2 induces an enormous amount of trapped electron density of an order of 1014 cm−2 near the interface between the FE-HfO2 and interfacial layer, which in turn screens the electric flux from polarization. We examine how electron trapping affects the device operation particularly the polarization switching mechanism, retention characteristics, endurance characteristics, and read-after-write delay. The asymmetric behavior of electron and hole trapping in FeFETs and its impact on the device operation are also discussed. We review several approaches based on different operations, device structure modification, and material engineering to mitigate anomalous electron trapping and improve the device characteristics of FeFETs. [ABSTRACT FROM AUTHOR]

We describe recent experiments using a SuperCDMS high-voltage single-charge sensitive (HVeV) detector illuminated with an ultraviolet LED (275 nm) and a monochromatic laser (650 nm) using a dual-fiber optic system installed in a small dilution refrigerator at Stanford University. We observed a population of fluorescence background events after UV exposure but not after exposure to the laser source. The fluorescence was likely due to scattered UV photons absorbed outside the detector. We discuss the possibility of fluorescence being a contributor to the low energy excess background observed in above-ground Dark Matter experiments. [ABSTRACT FROM AUTHOR]

Flash memories are the preferred choice for data storage in portable gadgets. The charge trapping nonvolatile flash memories are the main contender to replace standard floating gate technology. In this work, we investigate metal/blocking oxide/high-k charge trapping layer/tunnel oxide/Si (MOHOS) structures from the viewpoint of their application as memory cells in charge trapping flash memories. Two different stacks, HfO2/Al2O3 nanolaminates and Al-doped HfO2, are used as the charge trapping layer, and SiO2 (of different thickness) or Al2O3 is used as the tunneling oxide. The charge trapping and memory windows, and retention and endurance characteristics are studied to assess the charge storage ability of memory cells. The influence of post-deposition oxygen annealing on the memory characteristics is also studied. The results reveal that these characteristics are most strongly affected by post-deposition oxygen annealing and the type and thickness of tunneling oxide. The stacks before annealing and the 3.5 nm SiO2 tunneling oxide have favorable charge trapping and retention properties, but their endurance is compromised because of the high electric field vulnerability. Rapid thermal annealing (RTA) in O2 significantly increases the electron trapping (hence, the memory window) in the stacks; however, it deteriorates their retention properties, most likely due to the interfacial reaction between the tunneling oxide and the charge trapping layer. The O2 annealing also enhances the high electric field susceptibility of the stacks, which results in better endurance. The results strongly imply that the origin of electron and hole traps is different—the hole traps are most likely related to HfO2, while electron traps are related to Al2O3. These findings could serve as a useful guide for further optimization of MOHOS structures as memory cells in NVM. [ABSTRACT FROM AUTHOR]

Total-ionizing-dose (TID) effects are investigated in a highly-scaled gate-all-around (GAA) FET technology using Si nanowire channels with a diameter of 8 nm. n- and p-FETs are irradiated up to 300 Mrad(SiO2) and annealed at room temperature. TID effects are negligible up to 10 Mrad(SiO2). At ultrahigh doses, the TID degradation depends on the irradiation bias condition, with more severe effects observed in longer channel devices. The worst case irradiation condition is when positive bias is applied to the gate. Threshold-voltage shifts are caused by H+-driven generation of interface traps at the oxide/channel interface. In contrast, FETs irradiated under negative gate bias are dominated by transconductance loss and increases of low-frequency noise, suggesting the activation of border traps. Enhanced off-leakage current is observed in n-FETs due to charge trapping in shallow-trench isolation, and in p-FETs due to trap-assisted recombination at STI sidewalls and/or spacer dielectrics at drain/bulk junctions. [ABSTRACT FROM AUTHOR]

The ferroelectric field-effect transistor (FeFET) is a promising candidate for emerging memory. However, data retention loss is a key issue. One reason for the data retention loss is the depolarization field (${E}_{dep}$). In this work, we theoretically investigate ${E}_{dep}$ of ferroelectric transistors with the metal/Hf0.5Zr0.5O2/SiO2/Si substrate (MFIS) gate structure considering the minor loop and charge trapping effect at the ferroelectric/interlayer interface. We find that ${E}_{dep}$ increases first and then decreases with the increased interlayer thickness (${t}_{IL}$). The charge trapping phenomenon will decrease ${E}_{dep}$ and make ${t}_{IL}$ at which ${E}_{dep}$ reaches the peak value larger. To design a ferroelectric transistor considering both the depolarization field and the memory window, different schemes about how to choose suitable interlayer and ferroelectric layer thicknesses in three different regions need to be adopted. [ABSTRACT FROM AUTHOR]

A tunnel-oxide-free GaN-based non-volatile memory (NVM) device is proposed to untangle the trilemma among speed, retention, and endurance in the implementation of conventional NVM. The program and erase (P/E) are based on bipolar charge injection controlled by individual junction barriers, whereas the data retention relies on bipolar charge trapping in an interfacial charge storage layer. The wide bandgap energy of GaN allows the formation of deep-level traps at a dielectric/GaN interface and high junction barriers in GaN, both of which benefit long-term retention. As such, the GaN-based NVM device could get rid of the tunnel oxide, thereby enabling faster P/E processes and facilitating to decouple the enhancement of endurance from that of speed and retention. The proposed device demonstrates a P/E time of 100 ns, endurance over 106 cycles, and long retention time. [ABSTRACT FROM AUTHOR]

Metal–organic framework (MOF) is an emerging important class of functional materials in the fields of information storage, wearable electronics and optoelectronic devices. The interaction of electrons or holes with MOFs is important for the systematic exploration of MOFtronics and to investigate the related structure–performance correlation. Herein, MOF flat nanosheets of copper tetrakis(4‐carboxyphenyl)porphyrin with sub‐10 nanometer scale in thickness are employed as the charge‐trapping layer in organic field‐effect floating‐gate transistor memory device fabricated by an air–liquid interfacial assembly and subsequent stamping operation. As charge trapping sites, MOF nanosheets with ultrathin nanoporous arrays significantly improve in comparison with the memory device using its counterpart ligand of tetrakis(4‐carboxyphenyl)porphyrin as the trapping elements. As compared to the reported widely applied nanofloating gate materials of gold nanoparticles, graphene, or macromolecular nanomaterials, a short pulse (≈20 ms) on the device gets a considerable memory window of ≈37.5 V at a programming voltage of ‐80 V, with a retention time longer than 104 s and good ON/OFF ratio of >103. Furthermore, the hybrid structure composed of metal and organic components endows it with electron and hole trapping capability. This work could push forward the fundamental research of organic–inorganic–hybrid electronics in future microelectronic research. [ABSTRACT FROM AUTHOR]

Metal–organic framework (MOF) is an emerging important class of functional materials in the fields of information storage, wearable electronics and optoelectronic devices. The interaction of electrons or holes with MOFs is important for the systematic exploration of MOFtronics and to investigate the related structure–performance correlation. Herein, MOF flat nanosheets of copper tetrakis(4‐carboxyphenyl)porphyrin with sub‐10 nanometer scale in thickness are employed as the charge‐trapping layer in organic field‐effect floating‐gate transistor memory device fabricated by an air–liquid interfacial assembly and subsequent stamping operation. As charge trapping sites, MOF nanosheets with ultrathin nanoporous arrays significantly improve in comparison with the memory device using its counterpart ligand of tetrakis(4‐carboxyphenyl)porphyrin as the trapping elements. As compared to the reported widely applied nanofloating gate materials of gold nanoparticles, graphene, or macromolecular nanomaterials, a short pulse (≈20 ms) on the device gets a considerable memory window of ≈37.5 V at a programming voltage of ‐80 V, with a retention time longer than 104 s and good ON/OFF ratio of >103. Furthermore, the hybrid structure composed of metal and organic components endows it with electron and hole trapping capability. This work could push forward the fundamental research of organic–inorganic–hybrid electronics in future microelectronic research. [ABSTRACT FROM AUTHOR]

This article investigates the fin- and finger-number dependence of the total ionizing dose (TID) degradation in 16-nm bulk Si FinFETs at ultrahigh doses. n- and p-FinFETs designed with different numbers of fins and fingers are irradiated up to 500 Mrad(SiO2) and then annealed for 24 h at 100 °C. The TID responses of nFinFETs are insensitive to the fin number, as dominated by border and interface trap generation in shallow trench isolation (STI) and/or gate oxide. However, pFinFETs show a visible fin-number dependence with worst tolerance of transistors with the smallest number of fins. The fin number dependence may be related to a larger charge trapping in STI located at the opposite lateral sides of the first and last fins. In addition, both n- and p-FinFETs exhibit an almost TID insensitivity to the finger number. During the design of integrated circuits, the TID tolerance of electronic systems can be enhanced by preferably using transistors with a higher number of fins than fingers. [ABSTRACT FROM AUTHOR]

In this work, a comprehensive study of charge trapping and de-trapping dynamics is performed on n-channel ferroelectric field-effect transistors (nFeFETs) and pFeFETs. It is discovered that: 1) the degree of charge trapping depends on the substrate that nFeFETs exhibit significant electron trapping but negligible hole trapping during memory write while pFeFETs exhibit much less electron trapping but significant hole trapping when heavily stressed; 2) due to enhanced electric field in the interlayer and semiconductor, the like initial polarization states (i.e., initialized by a pulse of the same polarity as the write pulse) could exacerbate charge trapping induced by the write pulse; 3) electron trapping is fully recoverable while hole trapping shows a semi-permanent component which involves interface trap generation; and 4) less significant charge trapping in pFeFETs allows immediate read-after-write at normal operating conditions. [ABSTRACT FROM AUTHOR]

We investigate the charge trapping during endurance fatigue of FeFET with TiN/Hf0.5Zr0.5O2/SiO2/Si (MFIS) gate structure. We propose a method of experimentally extracting the number of trapped charges during the memory operation, by measuring the charges in the metal gate and Si substrate. We verify that the amount of trapped charges increases during the endurance fatigue process. This is the first time that the trapped charges are directly experimentally extracted and verified to increase during endurance fatigue. Moreover, we model the interplay between the trapped charges and ferroelectric polarization switching during endurance fatigue. Through the consistency of experimental results and simulated data, we demonstrate that as the memory window (MW) decreases: 1) the ferroelectric characteristic of Hf0.5Zr0.5O2 is not degraded; 2) the trap density in the upper bandgap of the gate stacks increases; and 3) the reason for MW decrease is increased trapped electrons after program operation but not related to hole trapping/detrapping. Our work is helpful to study the charge trapping behavior of FeFET and the related endurance fatigue process. [ABSTRACT FROM AUTHOR]

TCAD modeling of the dynamic threshold voltage shift (hysteresis) occurring under fast sweeping characterization in Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) is reported, to the best of our knowledge, for the first time. Dynamic ${V}_{\text{TH}}$ hysteresis has been first experimentally characterized under different sweeping times, temperatures, and AlGaN barrier configurations. Then, TCAD simulations have been carried out, reproducing the experimental evidences and understanding the microscopic mechanisms responsible for such effect. In particular, nonlocal tunneling models implemented in Sentaurus TCAD, defined at the gate Schottky contact and assisted by traps in the AlGaN barrier layer, have been adopted and properly tuned against experiments. Results show that the dynamic ${V}_{\text{TH}}$ hysteresis is mainly caused by the time-dependent hole charging/discharging processes in the floating p-GaN layer, which are governed by the Schottky and AlGaN barrier leakage current components. [ABSTRACT FROM AUTHOR]

A new charge-trapping nonvolatile memory (NVM) with a fully same structure to thin-film transistor (TFT) is investigated. Different from the conventional NVM with block layer/charge-trapping layer/tunneling layer stack for charge storage, this NVM uses the metal-hydroxyl (M-OH) defect at the back channel for charge storage, which forms by the reaction of IGZO with moisture and acts as acceptor-like deep-level traps. Devices with various M-OH contents are prepared by changing thermal treatment. The device with high M-OH content displays good NVM performance in terms of its large memory window (1.5 V at ±10 V, 1s), high program/erase speeds (1.1 V at 10 V, 1 ms) and good data retention (78.9% retention after 10 years); for comparison, the device with low M-OH content exhibits good TFT characteristics in terms of its small sub-threshold swing (226 mV/dec), high carrier mobility (8.1 cm2/V.s) and good electrical stability (memory window ~ 0.2 V at ±10 V, 1s). Since the NVM and TFT have the same structure, both the devices can be simultaneously prepared combined with an extra treatment to modulate the M-OH content at the back channel, thus contributing to system-on-panel development. [ABSTRACT FROM AUTHOR]

A novel strong physical unclonable function (PUF), called Probability-based PUF (Prob-PUF), is proposed using the stochastic process of trap emission in nano-scaled transistors. For the first time, the information of trap emission probability is used in the PUF design. This new approach offers ideal immunity to machine learning (ML) attacks. Since Prob-PUF only stores a mathematical model, it naturally avoids the dilemma between the requirement of a large number of challenge-response pairs (CRPs) and the limited storage space, making it a potential solution for future secure storage. [ABSTRACT FROM AUTHOR]

We report the temperature-dependent operation of back-end-of-line (BEOL) compatible amorphous indium-gallium-zinc-oxide (${a}$ -IGZO) ferroelectric thin-film transistors (FeTFTs) with a large memory window (MW) more than 3 V. Our ${a}$ -IGZO FeTFTs have a metal–ferroelectric–metal–insulator–semiconductor (MFMIS) stru- cture with Zr-doped HfO2 (HZO) as the ferroelectric layer. Characteristics of ${a}$ -IGZO FeTFTs are investigated in the temperature range of −40 °C to 100 °C. We found that: Firstly, the remanent polarization (${P}_{\text {r}}$) of the HZO film increases with $2{P}_{\text {r}}$ from $\sim 35~ {\mu }\text{C}$ /cm2 at −40 °C to $\sim 40~ {\mu }\text{C}$ /cm2 at 100 °C. Secondly, enhancement in MWs at high temperatures is observed, achieving MWs larger than 3.5 V when the temperature is higher than 60 °C. Thirdly, for the threshold voltage (${V}_{\text {TH}}$) at high temperatures, there is a competition between the negative shift caused by higher carrier concentration in the ${a}$ -IGZO channel and positive shift due to the charge trapping at the floating gate in the MFMIS structure. This could be explored to realize good ${V}_{\text {TH}}$ stability. [ABSTRACT FROM AUTHOR]

In this letter, p-type ferroelectric field-effect-transistors (FeFETs) based on HfO2 and embedded in GlobalFoundries 28 nm bulk high- ${k}$ metal gate (HKMG) technology (28SLPe) are systematically investigated and compared to their n-type counterparts. We show that the two device types, based on Si channel, exhibit a symmetric memory window (MW) and very similar switching behavior, yet profoundly different trapping kinetics. In contrast to n-FeFETs, p-FeFETs display a full MW immediately after the write operation and apparently no parasitic electron trapping. Based on this, we demonstrate an immediate read-after-write operation. Finally, we illustrate how slight structural changes of the gate stack, such as the introduction of the SiGe channel material, can enhance charge trapping and nullify the above-mentioned advantages. [ABSTRACT FROM AUTHOR]

Organic thin film transistor (OTFT) based nonvolatile memory has made significant progress due to its biocompatibility, flexibility, and low cost, in which ferroelectric transistor memory and floating gate transistor memory play the main roles in organic nonvolatile transistor memory. Here, a novel layered hybrid structure OTFT nonvolatile memory is invented by combining ferroelectric poly(vinylidene fluoride‐co‐trifluoroethylene) P(VDF‐TrFE) with a floating gate layer utilizing CdSe/ZnS quantum dots (QDs), which integrates the advantages of ferroelectric memory and floating gate memory. The core–shell structured CdSe/Zns QDs are acted as robust charge trapping centers due to their band structure similar to a quantum well, preventing the back diffuse of trapped charges, while P(VDF‐TrFE) provides additional polarized electric field to modulate the capture of charge. The resultant devices exhibit high on‐state current (≈10−5 A), low off‐state current (≈10−10 A), excellent switch ratio (≈105), and retention characteristic (>104 s). Furthermore, a superior memory window, more than 85.6% of scanning voltage range, higher than most reported organic transistor memories, is achieved, which endows the device wide operating condition and significant discrimination between on and off state. The fine‐structured OTFT memory opens up a unique path for desirable memory to meet the growing demand of microelectronic industry. [ABSTRACT FROM AUTHOR]

We study the impact of different interlayers (ILs) and ferroelectric materials on charge trapping during the endurance fatigue of Si ferroelectric field effect transistor (FeFET) with TiN/HfxZr1-xO2/ interlayer/Si (MFIS) gate-stack. We have fabricated FeFET devices with different interlayers (SiO2 or SiON) and HfxZr1-xO2 materials (${x} =0.75$ , 0.6, 0.5) and directly extracted the charge trapping during endurance fatigue. We find that: 1) under the same equivalent oxide thickness (EOT) condition, the increase of dielectric constant and interlayer thickness suppresses charge trapping and improves the endurance characteristics; 2) charge trapping effect is experimentally verified to be the origin of endurance fatigue; and 3) as the spontaneous polarization (${P}_{\text {s}}{)}$ of the HfxZr1-xO2 decreases from $25.9~ \boldsymbol {\mu } \text{C}$ /cm2 (Hf0.5Zr0.5O2) to $20.3~ \boldsymbol {\mu } \text{C}$ /cm2 (Hf0.6Zr0.4O2), the charge trapping behavior decreases, resulting in the slow degradation rate of memory window (MW) during program/erase cycling; in addition, when ${P}_{\text {s}}$ further decreases to $8.1~ \boldsymbol {\mu }\text{C}$ /cm2 (Hf0.75Zr0.25O2), the initial MW nearly disappears (only ~0.02 V). Thus, the reduction of ${P}_{\text {s}}$ could improve endurance characteristics. On the contrary, it can also reduce the MW. Our work helps design the MFIS gate-stack to improve endurance characteristics. [ABSTRACT FROM AUTHOR]

In this work, we developed the voltage-transient method to characterize the properties of traps in AlGaN/GaN high-electron-mobility transistors (HEMTs) in the OFF-state. By monitoring the drain voltage transients of the HEMTs at various temperatures, three types of trapping mechanism were identified: 1) buffer charge trapping, which occurred on a timescale of approximately 1 ms; 2) charge trapping in the AlGaN layer at the gate–drain edge with the energy level (${E}_{a}$) of approximately 0.54 eV; and 3) surface charge trapping with ${E}_{a}$ of approximately 0.28 eV. In particular, we extracted accurate amplitudes for the first two trapping behaviors and studied the dependence of the trapping effect on the filling bias conditions. The results showed that the buffer charge trapping was primarily affected by the drain voltage, whereas the charge trapping on the drain side of the gate was affected by both the drain and gate voltages; these results were verified by drift-diffusion simulations. In addition, we observed the third trapping behavior, which was apparent in the measurement window beyond 308 K, thus demonstrating the advantages of our method for correctly and effectively monitoring the changes in the peaks in the time constant spectrum. [ABSTRACT FROM AUTHOR]

Artificial photosynthesis of alcohols from CO2 is still unsatisfactory owing to the rapid charge relaxation compared to the sluggish photoreactions and the oxidation of alcohol products. Here, we demonstrate that CO2 is reduced to methanol with 100 % selectivity using water as the only electron donor on a carbon nitride‐like polymer (FAT) decorated with carbon dots. The quantum efficiency of 5.9 % (λ=420 nm) is 300 % higher than the previously reported carbon nitride junction. Using transient absorption spectroscopy, we observed that holes in FAT could be extracted by the carbon dots with nearly 75 % efficiency before they become unreactive by trapping. Extraction of holes resulted in a greater density of photoelectrons, indicative of reduced recombination of shorter‐lived reactive electrons. This work offers a strategy to promote photocatalysis by increasing the amount of reactive photogenerated charges via structure engineering and extraction before energy losses by deep trapping. [ABSTRACT FROM AUTHOR]