Search

Examines electron transport properties through indium arsenide quantum dots in modulation doped structures. Drain current modulation with respect to gate voltage in the material; Measurement of valley current energy gaps and voltage difference between drain current peaks; Use of the quantum dot charging energy as an explanation basis of the gaps.

Atomic layer deposited (ALD) tantalum nitride (TaxNy) is evaluated as a barrier against aluminum inside gate metal stacks of metal-oxide-semiconductor field effect transistor (MOSFET) devices. When deposited on hygroscopic oxides, like HfO2, amorphous tantalum nitride (a-TaxNy) is obtained, while deposition on Si or TiN results in polycrystalline Ta3N5. The low conductivity of both phases is not attractive for gate metal applications; however, a-TaxNy is crystallized to bixbyite Ta2N3 at 500 °C, improving its conductivity to ∼130 Ω−1 cm−1. For thicknesses below 10 nm, crystallization did not happen, but thin a-TaxNy barriers still obtain conductivity improvements to ∼500 Ω−1 cm−1 when Al diffuses into the film. In metal gate stacks, a-TaxNy screens the low work function of ALD TiAl more effectively than TiN. A barrier thickness reduction of 50% is achieved for n-MOSFET devices with an effective work function at 4.2–4.3 eV and low gate leakage. Slower diffusion of Al into TaxNy is observed by secondary ion mass spectroscopy; however, the cause of EWF lowering as a result of Al diffusion could not be confirmed. Instead, restoration of high EWF after removal of TiAl occurs, enabling an NMOS-first process integration with the use of 1 nm thin TaxNy barriers. [ABSTRACT FROM AUTHOR]

• LVT and (U)HVT pMOS and nMOS device flavors with p- and n-WFM's are compared in terms of performance and reliability. • LVT flavors (pMOS w/ p -WFM and nMOS w/ n- WFM) show best performance (mobility and drive current) and best BTI reliability. • TiAl induces oxygen-scavenging, yielding a ∼1Å thinner EOT, a larger density of O-vacancies, and positive interface charge. • The fixed positive interface charge induced by TiAl is identified as the cause of enhanced NBTI in (U)HVT pMOS. • The PBTI of (U)HVT nMOS w/ p -WFM is found to be enhanced due to the additional contribution of deep HfO 2 defects. • These deep HfO 2 traps are instead kept in equilibrium by the gate Fermi level in the presence of a n -WFM (nMOS LVT). • An unified Comphy model is proposed to reproduce the PBTI and NBTI trends in nMOS and pMOS with different gate WFM. • Guidelines for correct multi- V th gate stack BTI benchmarking based on accelerated RVS test are provided. Multi- V th CMOS device technologies have become standard for System-on-Chip designs. In Replacement Gate technologies, distinct device V th 's are achieved by deploying different work function metal stacks, and thus concerns exist about the possible chemical interaction of different gate metals with the underlying dielectrics potentially affecting the device performance and reliability. We present a comprehensive study, comprising both electrical measurements and simulations, carried out on a planar transistor platform with state-of-the-art gate stacks. Two different metal stacks are deployed to fabricate low- V th and ultra-high V th pMOS and nMOS device flavors. The study provides fundamental insights on the impact of TiAl-based gate metal on EOT, gate leakage, interface quality, carrier mobility, short channel performance, PBTI and NBTI reliability. [ABSTRACT FROM AUTHOR]

Abstract: As an alternative to W contacts currently used in MOSFETs for DRAM, Cu contacts using self-aligned Ta-silicide and Ta-based barrier were studied experimentally. The silicidation of PVD Ta layers was studied first on 300mm blanket Si wafers. The developed method was applied to patterned wafers in the contacts, that land on poly gate and active areas of NMOS, with a sequence including the PVD of Ta, a silicidation annealing, a Ta-based Cu diffusion barrier and a Cu seed for plating the Cu plug. X-ray diffraction (XRD), X-ray reflection (XRR) and sheet resistance tests of the blanket wafers show that a Ta layer of about 10nm reacts with Si substrate and forms TaSi2 at 650°C in a reducing ambient. Cross-sectional SEM observation reveals that the selected processing flow fills the 90nm contacts. Top-view SEM observation on the samples after 420°C sintering demonstrates that the Cu diffusion barrier is effective. I on–I off curves of the devices show a performance for NMOS comparable to the reference samples which use Ni(Pt)Si and the same barrier and Cu contacts, indicating that the stack of the barrier/TaSi2/p-type Si has a contact resistance comparable to the barrier/Ni(Pt)Si/p-type Si. [Copyright &y& Elsevier]

The DC and low-frequency noise performance of an array of 800 parallel Forksheet MOSFETs were investigated by performing measurements over a wide temperature range from 300 K to 4 K. The array structure allowed to measure a representative average performance of the devices and provided a large effective area for 1/f noise analysis. Results showed an improvement in the saturation drain current when going from room temperature to cryogenic temperatures, with the subthreshold swing saturating around 100 K and the threshold voltage shifting by approximately 150 mV, following similar trends observed in Silicon cryogenic electronics. Additionally, the study confirms that the noise at cryogenic temperatures does not follow the commonly assumed linear scaling with temperature. This deviation from the linear scaling has been associated with the presence of tail states at the interface in bulk and silicon-on-insulator (SOI) devices. These results suggest that the excess 1/f noise in this advanced device architecture is not related to the device architecture but rather to the microscopic material properties of semiconductor/dielectric interfaces. • DC and low-frequency noise characterization of Forksheets from 300 K to 4 K. • 1/f noise at cryogenic temperatures does not scale linearly with temperature. • 1/f noise at low temperatures originates from the semiconductor/dielectric interface. [ABSTRACT FROM AUTHOR]

This article reports Si-passivated Ge nFinFETs with significantly improved GmSAT/SSSAT and positive bias temperature instability (PBTI) reliability enabled by an improved replacement metal gate (RMG) high-k last process. SiO2 dummy gate oxide (DGO) deposition on Ge fin is shown to form (Six)Ge1-xOy, which is, compared to a pure SiO2, more difficult to remove completely during the dry clean prior to the gate-stack formation. By extending the DGO removal clean, improved PBTI reliability, reduced DIT, and increased electron mobility are demonstrated. Moreover, by suppressing the Ge channel oxidation through the choice of less-oxidizing DGO or inserting an Si-cap layer prior to the DGO deposition, a greatly improved long-channel electron mobility is obtained at a scaled fin width. Finally, together with the PBTI maximum VOV of 0.13 V, the best GmSAT/SSSAT of 5.4 is achieved, which is today’s record value among the sub-100-nm-Lg n-channel Ge Fin and gate-all-around nanowire FETs. These results clearly show the importance of the pre-gate-stack channel surface preparation on the scaled Ge FinFETs to benefit from a previously optimized Si-passivated Ge gate-stack. [ABSTRACT FROM AUTHOR]

In this work, we have studied gate length (L gate ) scalability of Si 0.55 Ge 0.45 Implant Free Quantum Well (IFQW) pFET with raised and embedded Si 0.75 Ge 0.25 source/drain structures. Although embedded SiGe device shows higher I dsat which can be attributed to thinner T inv (more scavenging of High-k interfacial layer), raised SiGe device has better short channel control than embedded SiGe device thanks to shallower junction depth. Raised SiGe device can scale down L gate by 4 nm compared to embedded SiGe device while maintaining identical I off . This results in superior intrinsic delay in raised SiGe device. [ABSTRACT FROM AUTHOR]

Epitaxial growth of strained and defect free SiGe layers grown with disilane and digermane was investigated. This precursors set allows to cover a broad range of Ge concentration (15–65%) at low temperatures (400–550 °C). It was shown that change of carrier gas (from H 2 to N 2 ) does not increase SiGe growth rate but significantly reduces Ge concentration. Increase of total process pressure considerably reduces SiGe growth rate which is attributed to peculiarities of digermane decomposition and influence of hydrogen surface passivation on disilane decomposition. It was shown that both disilane and digermane can be successfully combined with conventional precursors like silane and germane. These experiments suggested that digermane decomposition is the main driver of the growth rate increase during SiGe growth. Based on the presented data we demonstrated growth of different SiGe/Si and SiGe/Ge stacks with high quality necessary for production of gate all around field effect transistors. [ABSTRACT FROM AUTHOR]

SiGe quantum-well pMOSFETs have recently been introduced for enhanced performance of transistors. Quite surprisingly, a significant reduction in negative bias temperature instability (NBTI) was also found in these devices. Furthermore, a stronger oxide field acceleration of the degradation in SiGe devices compared with Si devices was reported. These observations were speculated to be a consequence of the energetical realignment of the SiGe channel with respect to the dielectric stack. As these observations were made on large-area devices, only the average contribution of many defects to NBTI could be studied. In order to reveal the microscopic reasons responsible for the improved reliability, a detailed study of single defects is performed in nanoscale devices. To provide a detailed picture of single charge trapping, the step-height distributions for different device variants are measured and found to follow a unimodal and bimodal distribution. This finding suggests two conducting channels, one in the SiGe and one in the thin Si cap layer. We, furthermore, demonstrate that similar trap depth distributions are present among the device variants supported by a similar stress bias dependence of the capture times of the identified single defects. We conclude that NBTI is primarily determined by the dielectric stack and not by the device technology. [ABSTRACT FROM AUTHOR]

The susceptibility of conventional silicon p-channel MOS transistors to negative bias temperature instabilities (NBTIs) is a serious threat to further device scaling. One possible solution to this problem is the use of a SiGe quantum-well channel. The introduction of a SiGe layer, which is separated from the insulator by a thin Si cap layer, not only results in high mobilities but also superior reliability with respect to NBTI. In part one of this paper, we provide experimental evidence for reduced NBTI by thoroughly studying single traps in nanoscale devices. In this paper, we present detailed TCAD simulations and employ the four-state nonradiative multiphonon model to determine the energetical and spatial positions of the identified single traps. The found trap levels agree with the defect bands estimated in large-area devices. Our conclusions are also supported by the observation of similar activation energies for defects present in transistors of various device geometries. From the calibrated TCAD simulations data, an impressive boost of the time-to-failure for the SiGe transistor can be predicted and explained. [ABSTRACT FROM AUTHOR]

This paper reviews some of the key doping strategies pursued for scaled finFET devices fabrication, addressing several of the critical integration challenges faced by this device architecture with regard to junction engineering, parasitics and series resistance control and their impact on device performance, reliability and variability. We will therefore look into the extendibility possibilities of using conventional doping techniques such as ion implantation, explore the use of novel methods to enable conformal doping of the thin body of the devices, and also evaluate junctionless vs. inversion-mode type of transistors for gate-all-around nanowire FETs, which can essentially be considered as the ultimate scaling limit of triple-gate finFETs. [ABSTRACT FROM AUTHOR]

Integration of Si 0.30 Ge 0.70 in the Source/Drain (S/D) areas of metal oxide semiconductor transistors built according to 14 nm technological node rules has been shown. SiGe properties and growth peculiarities are presented and elaborated. In order to preserve the fin structures during a pre-epitaxy surface preparation, the H 2 bake pressure had to be increased to 19,998 Pa at 800 °C. Influence of this bake on the Si recess in the S/D areas is presented. Excellent quality of both the raised and the embedded Si 0.30 Ge 0.70 was demonstrated by transmission electron microscopy inspections. Energy-dispersive X-ray spectroscopy measurement showed two stages of SiGe growth for the embedded case: first with a lower Ge content at the beginning of the deposition until the (111) facets are formed, and second with a higher Ge content which is governed by the growth on (111) planes. Nano-beam diffraction analysis showed that SiGe grown in the S/D areas of p-type metal-oxide-semiconductor field-effect transistor is fully elastically relaxed in the direction across the fin and partially strained along the fin. Finally, a strain accumulation effect in the chain of transistors has been observed. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate a High-k Metal Gate (HKMG) Implant Free Quantum Well (IFQW) SiGe-pFET device used as a DRAM periphery device. Using a c:Si 0.55 Ge 0.45 channel and embedded e:Si 0.75 Ge 0.25 source/drain (S/D), a very significant source current of 625 μA/μm @ I OFF =100 pA/μm (at supply voltage V DD =−1 V) is demonstrated. The current improvement compared to DRAM compatible unstrained Silicon baseline technology (featuring HKMG) is large, and IFQW transistors are also competitive with regards to Strained Si devices. In particular, IFQW have a specific potential for Sense Amplifiers, with a demonstrated very good drive current/transconductance boost in the range of targeted gate lengths and excellent matching properties. [ABSTRACT FROM AUTHOR]

Highlights: [•] A NiPt silicide stable with long 600 and 800°C anneals, as required by DRAM periphery. [•] Thermally stable silicide by pre-amorphisation+C implant+laser anneal. [•] TSS successfully integrated in low voltage CMOS HKMG devices suitable for DRAM PERI. [•] Thermal stability can be obtained using a spike anneal rather than a laser anneal. [ABSTRACT FROM AUTHOR]

The scaling behavior of Gd- and Al-doped HfO2 films as gate dielectrics in metal-oxide-semiconductor (MOS) capacitors was studied. For equivalent oxide thicknesses (EOTs) in the range of 10Å, crystallized Gd:HfO2 showed higher leakage current densities than crystallized Al:HfO2, with undoped HfO2 in between. Ultimately, the scalability of Al:HfO2 was limited by the ability to crystallize the films at a given thermal budget. As a result, for post-deposition annealing at 800 C, the EOT of Al:HfO2 based MOS capacitors was limited to ~8Å . However, for such an EOT, leakage current densities were reduced by about 100× with respect to HfO2. This demonstrates the high potential of Al:HfO2 for low-standby-power MOS devices. [ABSTRACT FROM AUTHOR]

Abstract: In this work, the possibility of integration of High-k/Metal Gate (HKMG), Replacement Metal Gate (RMG) gate stacks for low power DRAM compatible transistors is studied. First, it is shown that RMG gate stacks used for Logic applications need to be seriously reconsidered, because of the additional anneal(s) needed in a DRAM process. New solutions are therefore developed. A PMOS stack HfO2/TiN with TiN deposited in three times combined with Work Function metal oxidations is demonstrated, featuring a very good Work Function of 4.95eV. On the other hand, the NMOS side is shown to be a thornier problem to solve: a new solution based on the use of oxidized Ta as a diffusion barrier is proposed, and a HfO2/TiN/TaOX/TiAl/TiN/TiN gate stack featuring an aggressive Work Function of 4.35eV (allowing a Work Function separation of 600mV between NMOS and PMOS) is demonstrated. This work paves the way toward the integration of gate-last options for DRAM periphery transistors. [Copyright &y& Elsevier]

Abstract: This work presents a process to fabricate Bulk FinFETs with advancements in critical fabrication steps such as the shallow trench oxide recess and the adjustment of the fin height. These steps are accomplished with the adoption of Siconi™ Selective Material Removal (SMR™) in the fabrication flow. FinFETs obtained with this new integration scheme were tested in a co-fabrication process flow proposed to integrate planar CMOS and Bulk FinFETs on the same wafer. Morphological and electrical results indicate perfectly filled trenches, a better fin height control and a Bulk FinFET static performance similar to planar CMOS. The 20nm wide fins are fabricated using 193nm illumination lithography followed by a series of trimming steps during the trench etching, the filling and a fin re-oxidation during the steam densification of the trench filling oxide. Trench depth is 300nm and the electrically active fin height is 40nm. [Copyright &y& Elsevier]

BACKGROUND AND PURPOSE Oxidative stress plays a critical role in liver fibrogenesis. Reactive oxygen species (ROS) stimulate hepatic stellate cells (HSCs), and ROS-mediated increases in calcium influx further increase ROS production. Azelnidipine is a calcium blocker that has been shown to have antioxidant effects in endothelial cells and cardiomyocytes. Therefore, we evaluated the anti-fibrotic and antioxidative effects of azelnidipine on liver fibrosis. EXPERIMENTAL APPROACH We used TGF-β1-activated LX-2 cells (a human HSC line) and mouse models of fibrosis induced by treatment with either carbon tetrachloride (CCl4) or thioacetamide (TAA). KEY RESULTS Azelnidipine inhibited TGF-β1 and angiotensin II (Ang II)-activated α1(I) collagen mRNA expression in HSCs. Furthermore, TGF-β1- and Ang II-induced oxidative stress and TGF-β1-induced p38 and JNK phosphorylation were reduced in HSCs treated with azelnidipine. Azelnidipine significantly decreased inflammatory cell infiltration, pro-fibrotic gene expressions, HSC activation, lipid peroxidation, oxidative DNA damage and fibrosis in the livers of CCl4- or TAA-treated mice. Finally, azelnidipine prevented a decrease in the expression of some antioxidant enzymes and accelerated regression of liver fibrosis in CCl4-treated mice. CONCLUSIONS AND IMPLICATIONS Azelnidipine inhibited TGF-β1- and Ang II-induced HSC activation in vitro and attenuated CCl4- and TAA-induced liver fibrosis, and it accelerated regression of CCl4-induced liver fibrosis in mice. The anti-fibrotic mechanism of azelnidipine against CCl4-induced liver fibrosis in mice may have been due an increased level of antioxidant defence. As azelnidipine is widely used in clinical practice without serious adverse effects, it may provide an effective new strategy for anti-fibrotic therapy. [ABSTRACT FROM AUTHOR]

Abstract: FinFET devices are one of the most promising candidates for enabling SRAM scaling beyond the 32nm technology node. This paper will describe the challenges faced when setting up the patterning processes in the front-end part of a 22nm node 6T-SRAM cell. Key in this work was achieving the required CD and profile target specs for the fin and the gate level. Also, the implant levels, though still a 450nm pitch, turned out to be more difficult than expected because of the underlying topography. All this work resulted in the first electrically functional 22nm node SRAM cell, with the contact and metal level exposed on the ASML EUV α-demo tool. [Copyright &y& Elsevier]

Abstract: In this paper we report on electrical demonstration of thermally stable Ni silicides. It has been shown that when a sacrificial Si1− x C x epilayer is grown in the source-drain areas of NMOS transistors prior to silicidation, Ni silicides can withstand a 30min anneal at 750°C and demonstrate excellent electrical performance. We have observed carbon segregation at the NiSiC/Si1− x C x interface which can explain the increased NiSiC thermal stability. We have experimentally demonstrated feasibility of CMOS device implementation of thermally stable Ni silicides. [Copyright &y& Elsevier]

We report on vertically stacked lateral nanowires (NW)/nanosheets (NS) gate-all-around (GAA) FET devices as promising candidates to obtain a better power-performance metric for logic applications for advanced sub-5 nm technology nodes, in comparison to finFETs. In addition, vertical NW/NS GAA FETs appear particularly attractive for enabling highly dense memory cells such as SRAMs (with improved read and write stability), and as the selector devices for ultra-scaled MRAMs with lower energy consumption values. These cells can be manufactured by a cost-effective, co-integration scheme with a triple-gate finFET or a lateral NW/NS GAA FET high-performance logic platform for increased on-chip memory content. [ABSTRACT FROM AUTHOR]