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A new kind of one-time password authentication scheme, directed one-time password authentication scheme, is presented in this paper. The distinguished feature of the directed authentication scheme is that only the specified verifier can validate the verifiee's genuine identity, without the help of this specified verifier, anyone else cannot verify it. One strong directed one-time password authentication scheme based on discrete logarithm is proposed in this paper and the security and performance of which are also analyzed. [ABSTRACT FROM AUTHOR]

The increasing power consumption levels of integrated circuits (ICs) have become a major concern of the semiconductor industry. Excessive power dissipation causes overheating, which can lead to soft errors or permanent damage. It also limits battery life in portable equipment. High power consumption can be reduced by properly increasing area. However, arbitrarily large area, namely high number of functional units (FU) in high-level view, dramatically increases IC cost. This paper describes a new dynamic-power aware High Level Synthesis data path approach that considers dynamic FU allocation while attempting to minimize area, power, or make a trade-off between them. The experimental results have shown that when the area is nearly the same, our approach delivers a 5.99% reduction in power consumption. And when the power consumption is nearly the same, a 11.81% reduction in total FU area occurs. And we can obtain different optimal power-area trade-off values by adjusting power and area ratios. [ABSTRACT FROM AUTHOR]

Built-In Self Test (BIST) techniques are commonly used as an efficient alternative to external testing in today's high-complexity VLSI chips since they provide on-chip test pattern generation and response verification. Among the BIST techniques, Built-In Logic Block Observation (BILBO) has been widely used in practice. Test patterns generated by BILBO structures target the detection of stuck-at faults. It has been shown that most common failure mechanisms that appear into current CMOS VLSI circuits cannot be modeled as stuck-at faults. These mechanisms, modeled by sequential (i.e., stuck-open and delay) faults models, require the application of two-pattern tests (vector pairs) in the circuit-under-test inputs. Single Input Change (SIC) pairs are pairs of patterns where the second pattern differs from the first in only one bit and have been successfully used for two-pattern testing. In this paper we present the BILBO-oriented SIC pair Generator technique that extends BILBO in order to generate SIC pairs; in this way, sequential faults are also detected. [ABSTRACT FROM AUTHOR]

New low-power design architecture based on low-swing voltage technique is proposed in this paper. A new CMOS inverter of three output-voltage levels is used to achieve this target. To verify the validity of the proposed technique, three different logic families are used. SPICE simulation results for the three logic families show that more than 45% power dissipation can be saved, without sacrifice the speed operation. Comparison results between the proposed technique and other techniques based on low-swing voltage, shown the superiority of our technique in reducing the power dissipation. Based on 2.4 V supply voltage, a 16 &zast; 16-bit multiplier is implemented by using the proposed technique in 0.25 μm silicon technology. [ABSTRACT FROM AUTHOR]

In this research paper, we propose an automatic segmentation method of multispectral magnetic resonance image (MRI) of the human brain using an information fusion approach through the framework of the possibility theory. The fusion process is summarized into three essential steps. First, a data is extracted from the various images and modeled in a common mathematical framework, in this step the fuzzy C-means (FCM) algorithm is chosen. The combination rule is used to combine this information in the second step. A final segmented image is the result of the last phase. Our experimental results using simulated brain MRI datasets show that the pro-posed approach overcome the impact of the noise and substantially improve the accuracy of image segmentation. [ABSTRACT FROM AUTHOR]

In this paper, an adaptive digital image watermarking technique using fuzzy gradient on DCT domain is presented. In our approach, the image is divided into separate blocks and the DCT is applied on each block individually. Then, the watermark is inserted in the transform domain and the inverse transform is carried out. We increase the robustness of the watermark by increasing the watermark strength. However, this reduces the fidelity of the watermarking scheme. This is because the fidelity and robustness of watermarking are generally in conflict with each other. To improve the fidelity, a new fuzzy-based method is introduced. In this method, a fuzzy gradient-based mask is generated from the host image. Then, as a post-processing stage, the generated mask is combined with the watermarked image. Experimental results show that the proposed technique has high fidelity as well as high robustness against a variety of attacks. [ABSTRACT FROM AUTHOR]

The study presented in this paper highlights an important issue that was subject for discussions and research about a decade ago and now have gained new interest with the current advances of grid computing and desktop grids. New techniques are being invented on how to utilize desktop computers for computational tasks but no other study, to our knowledge, has explored the availability of the said resources. The general assumption has been that there are resources and that they are available. The study is based on a survey on the availability of resources in an ordinary office environment. The aim of the study was to determine if there are truly usable under-utilized networked desktop computers available for non-desktop tasks during the off-hours. We found that in more than 96% of the cases the computers in the current investigation was available for the formation of part-time (night and weekend) computer clusters. Finally we compare the performance of a full time and a metamorphosic cluster, based on one hypothetical linear scalable application and a real world welding simulation. [ABSTRACT FROM AUTHOR]

This paper introduces a novel method of identifying better representatives of faulty cells in a memory map to help judge unrepairability and provide economical repair solutions. These representatives, called leading elements (LE), are classified into four primary types based on their characteristics. The proposed method primarily assigns the faulty cells without row or column complements as LE, making them more useful in judging unrepairability and providing economical repair solutions. Some initially identified LE are further replaced with suitable faulty cells for being LE. Experiments on many example maps show the distribution of LE in various sizes of memories with distinct numbers of faulty cells. Compared to the previous work, the improved procedure can identify 7.3% more LE, with only 1.5% additional run time. [ABSTRACT FROM AUTHOR]

Most of the FPGA's area and delay are due to routing. Considering routability at earlier steps of the CAD flow would both yield better quality and faster design process. In this paper, we discuss the metrics that affect routability in packing logic into clusters. We are presenting a routability-driven clustering method for cluster-based FPGAs. Our method packs LUTs into logic clusters while incorporating routability metrics into a cost function. Based on our routability model, the routability in timing-driven packing algorithm is analyzed. We integrate our routability model into a timing-driven packing algorithm. Our method yields up to 50% improvement in terms of the minimum number of routing tracks compared to VPack (16.5% on average). The average routing area improvement is 27% over VPack and 12% over t-VPack. [ABSTRACT FROM AUTHOR]

This paper presents an investigation of the design optimization in microstrip lines to reduce the crosstalk level using Fuzzy Logic. In microstrip lines length and spacing, termination conditions of interconnection and output impedance of gates are the major components that cause crosstalk. In order to design high speed printed circuit board (PCB) with optimum interconnection configuration, it is essential to reduce the crosstalk to its minimum tolerance level. A design methodology is proposed to correlate electrical parameters and physical configuration of lines to the crosstalk phenomena. This design is subsequently optimized using Fuzzy Logic to reduce the level of crosstalk. A set of experiments is carried out to demonstrate the capabilities of the design and optimization methods. The effect of the geometrical configuration of the lines on crosstalk, particularly the spacing, is highlighted. [ABSTRACT FROM AUTHOR]

Power consumption of multimedia applications executing on embedded cores is heavily dependent on data transfers between system memory and processing units. The purpose of this paper is to extend an existing power optimizing methodology based on data-reuse decisions, in order to determine the optimal solution in a rapid and reliable way. An analytical approach is proposed by extracting expressions for the number of accesses to each memory layer. Moreover, the design space is further reduced since these analytical expressions are calculated only for a subset of all transformations. The results concerning the power efficiency of data-reuse transformations are in agreement to those in previous studies. However, the exploration time of the design space is significantly reduced. The proposed methodology is also applied to the case of multiple parallel processing cores, proving that the relative effect of each transformation is independent on the number of processors and the applied memory architecture. [ABSTRACT FROM AUTHOR]

In 1992, a new spatial temporal computing idea had been proposed, the CNN Universal Machine. It turned out that a new paradigm in computing on image flows, a Universal Machine on Flows, has ignited the intellect of hundreds of researchers. Today, visual microprocessors based on this idea can perform about TeraOPS computing power and 10 000 frames per second. In this paper, after a brief description of the history of the invention, architectural advances, physical implementation, algorithmic developments, as well as the biology relevance, theoretical aspects, mission critical applications, and new directions are reviewed. [ABSTRACT FROM AUTHOR]

The aim of this paper is to investigate synchronization phenomena in arrays composed of locally interconnected chaotic circuits. Such arrays are often considered as generalized Cellular Nonlinear Networks. In our computer experiments we study in particular the phenomena of formation of synchronized spatial clusters. [ABSTRACT FROM AUTHOR]

This paper presents new criteria for the existence of stable equilibrium points in the total saturation region for cellular neural networks (CNNs). It is shown that the results obtained can be used to derive some complete stability conditions for some special classes of CNNs such as positive cell-linking CNNs, opposite-sign CNNs and dominant-template CNNs. Our results are also compared with the previous results derived in the literature for the existence of stable equilibrium points for CNNs. [ABSTRACT FROM AUTHOR]