AN EFFICIENT LOW-SWING MULTITHRESHOLD-VOLTAGE LOW-POWER DESIGN TECHNIQUE.

New low-power design architecture based on low-swing voltage technique is proposed in this paper. A new CMOS inverter of three output-voltage levels is used to achieve this target. To verify the validity of the proposed technique, three different logic families are used. SPICE simulation results for the three logic families show that more than 45% power dissipation can be saved, without sacrifice the speed operation. Comparison results between the proposed technique and other techniques based on low-swing voltage, shown the superiority of our technique in reducing the power dissipation. Based on 2.4 V supply voltage, a 16 &zast; 16-bit multiplier is implemented by using the proposed technique in 0.25 μm silicon technology. [ABSTRACT FROM AUTHOR]