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Addition and multiplication are some of the most broadly adopted arithmetic operations in a wide range of applications. This paper proposes new structures of approximate multipliers to optimize the area, delay, and power without affecting the accuracy metrics. Multipliers and adders play a significant role in the functioning of any digital circuit or system. The overall performance of a processor highly depends on the speed of adders and the energy consumption. In this paper, two types of compact error-tolerant approximate adders are designed and used along with approximate 4:2 compressors to improvise the efficiency of the approximate multipliers. The proposed approximate multipliers show good results when compared to the existing structures in terms of area, delay, power, and accuracy. The approximate multipliers are applied to image sharpening and image multiplication applications. The error-tolerant adder's performance is evaluated in the practical domain using the image blending application. Peak signal-to-noise ratio (PSNR) performance and the structural similarity index metric (SSIM) are used to assess the modeled designs. The proposed approximate multipliers and adders exhibit better performance in terms of PSNR and SSIM and are found to be an optimized design to apply effectively in various error-tolerant image processing applications. [ABSTRACT FROM AUTHOR]

In this research on range query technology for two-tiered wireless sensor networks, the existing researches still need improvement in privacy security and communication cost of the sensor node. In this paper, a security multi-dimensional range query protocol is proposed. The left 0-1 encoding mechanism (a new and optimized encoding mechanism), HMAC algorithm, and BASE64 encoding are employed to optimize the calculation of comparison factor. The encryption index chain is constructed by using AES algorithm to replace the long encryption constraint chain, so as to lower the energy consumption of computation and communication. The base station can verify the authenticity and integrity of query results on the basis of continuity of storage time and encryption index chain. The experiment has been conducted in the real systems. The protocol is compared and analyzed with the latest proposed Communication-Efficient Secure Range Queries (CSRQ). The results have shown that the proposed protocol can gain a better performance in terms of four aspects, i.e., the length of sensing data, the number of data collected in each cycle, the number of data dimensions and the number of sensor nodes in each unit. Meanwhile, compared with CSRQ, the communication cost of the proposed protocol is reduced by at least 10%. [ABSTRACT FROM AUTHOR]

In recent times, the virtual power plant (VPP) is gaining more attention in power system engineering due to its tremendous potential in enhancing sustainable urbanism, in which, it supplies clean energy from distributed generators. Electricity is deemed a basic requirement for future automotive and ultra-modern technologies. The deficiency of traditional energy resources and their complex generation process make the production cost of electricity increase dramatically. Moreover, traditional power distribution systems are encountering issues in distributing electrical energy to fulfill customer demands. Therefore, this paper proposes a novel power management system named 'the hybrid genetic local binary knowledge (HGLBK) algorithm' to manage power distribution in the transmission lines and to optimize the total operation cost of the network. The hybrid optimization algorithm effectively controls the load by supplying the surplus power load to the adjacent feeders thereby optimally selecting and placing the distributed energy resource (DER). The proposed concept is implemented at Kayathar, Tamil Nadu in India, and their real-time data are utilized for modeling the VPP. The proposed VPP concept is implemented in the IEEE-9 bus system and the performance of VPP is simulated using the MATLAB software. The performance of the proposed HGLBK algorithm is assessed by comparing its effectiveness with the existing approaches. [ABSTRACT FROM AUTHOR]

Capacitor mismatch plays an important part in the spurious-free dynamic range (SFDR) performance of high-resolution successive approximation register (SAR) analog-to-digital converters (ADCs). This paper presents a symmetric group control dynamic element matching (SGCDEM) method aiming at enhancing SFDR of SAR ADCs applied in biomedical applications. The proposed scheme symmetrically divides the capacitor array into four sub-DACs, using quantization results corresponding to each sub-DAC as rotary control codes to symmetrically control the rotation of the capacitors. In order to improve the energy efficiency and save chip area, the proposed method replaces the pseudo-random number generator (PRNG) with quantization results of ADC as the rotary control code. Moreover, split rotator technology is applied in the proposed scheme to reduce the number of multiplexers (MUX) used in the rotator, which introduces a low logic depth. The proposed architecture has been implemented on a 12-bit SAR ADC model in MATLAB in order to verify its performances. After taking a standard deviation of 1% for the unit capacitance into consideration, this method achieves above 77.3 dB SFDR, enabling to correct the SFDR by more than 23.6 dB compared with the structure without DEM. [ABSTRACT FROM AUTHOR]

The Underwater Wireless Sensor Network (UWSN) is capable of supporting a wide range of low-data-rate acoustic sensor networks, as well as scalability and energy-efficient routing algorithms. Furthermore, because of the lower bandwidth and longer propagation delays, energy consumption is a major concern with underwater networks. Because radio transmissions are unstable in deep water, a UWSN often communicates via acoustic channels. UWSN features create constraints on data packet transmission and energy-efficient routing. The hardest challenge is creating an effective routing protocol for UWSNs that uses sensor node localization. There have been several routing algorithms reported for identifying nodes via a localization process. This paper proposes a novel vector-based forwarding (NVBF) and efficient depth-based routing (DBR) protocol to provide robust, scalable, and energy-efficient routing. Efficient DBR is a stochastic model that can survive even in acoustic channels with substantial transmission loss. An adjacent node table is created to decrease the energy consumption and end-to-end delay by limiting the adjacent node request generated every single time. The redundant packet transmission is reduced by creating a packet queue which also minimizes the energy. The NVBF algorithm uses a random waiting time to overcome the collision that occurs while sending the acknowledgment packets. Based on the previous sender's depth and the depth of the own node, the DBR makes packet transmission decisions. The experiments are conducted using the NS3 simulator and the efficiency of the proposed approach is evaluated in terms of propagation delay, network lifetime, energy consumption, and delivery ratio. When compared to the existing techniques such as DBR, VBF, and energy-efficient DBR (EDBR), the proposed methodology offers improvement up to 40% and 30% in terms of propagation delay and delivery ratio. [ABSTRACT FROM AUTHOR]

Reliability and energy efficiency are two hostile objectives considered in designing task scheduling in most real-time multiprocessor systems on chip (MPSoC). Addressing and improving one of them may affect and degrade the efficiency of the other one and vice versa. In this paper, we intend to examine these challenges and ultimately achieve an optimal energy consumption and reliability state. This paper presents a novel scheduling technique that can adapt to the limitations of real-time systems and have optimal energy consumption and reliability. This is done by minimizing the overlap of tasks, adjusting the speed of processors and the number of backups of each task. The proposed scheme reduces energy consumption on average by 11% to 42% compared to the previous state-of-the-art techniques and keeps the reliability at a high level. [ABSTRACT FROM AUTHOR]

Wireless sensor networks' energy consumption is the major challenge to be handled. Clustering is one of the techniques majorly used for reducing energy consumption. During the course of time, many methodologies are being proposed and the existing ones are hybrid. Still, the energy can be reduced more. The scope of optimization is always there. Existing approaches either reduce energy consumption or work on routing or only on data gathering capabilities. But the technique proposed increases the lifetime of the wireless sensor network (WSN) by reducing energy consumption and improves routing efficiency. This paper proposes an approach based upon Fractal Clustering to improve the lifetime of the sensor nodes. The proposed approach named Enhanced Energy Efficient Fuzzy-based Fractal Clustering (EEFFC) algorithm optimizes the performance of WSN. First, fractal clustering is used on sensor nodes to find the location of the sensors. Then, a fuzzy inference system (FIS) is applied to results produced by fractal clustering. Applying FIS on cluster heads generated will optimize the results. As a result, the cost of data transmission will reduce, and hence, the lifetime of the network will improve. FIS generates multi-level clustering, which will result in a better routing path for sensor nodes. Hence, routing will also be improved. MATLAB 2020 is the simulation tool. The results of the simulation depict that EEFFC shows optimized results and it works better than LEACH, LEACH-SF, TEEN and DEEC. The energy consumption is being reduced by reducing the listening time of a node and by reducing the communication distance, for which clustering is optimized. The energy consumption has been reduced by 2% as compared to the algorithms it is compared with. Also, the node's time of death has been delayed by 3% in total. [ABSTRACT FROM AUTHOR]

A prerequisite to ensure the stability of the power supply system is suitable functioning of transmission line equipment. However, the increasing deployment of transmission lines in modern power systems has introduced significant challenges to line inspection. While deep learning-based image detection techniques have shown promise in improving the efficiency and accuracy of insulator detection, they often require substantial computational resources and energy. This limitation hinders the consistent guarantee of accuracy and real-time performance on resource-constrained drones. To address this issue, this paper investigates the co-optimization problem of energy consumption and analytic accuracy in insulator image detection on unmanned aerial vehicles (UAVs). We propose a latency-aware end-edge cooperative insulator detection task offloading scheme with high energy efficiency and accuracy that aims to achieve optimal performance. Initially, we conducted an experimental analysis to examine the influence of input image resolution on the accuracy and latency of the CNN-based insulation detection model. Subsequently, we develop a model that takes into account the latency, analytic accuracy and energy consumption for image detection task offloading. Finally, we formalized a nonlinear integer optimization problem and designed a particle swarm optimization (PSO)-based task offloading scheme to optimize task accuracy and energy consumption while adhering to latency constraints. Extensive experiments validated the effectiveness of the proposed end-edge cooperative insulator detection method in optimizing accuracy and energy consumption. [ABSTRACT FROM AUTHOR]

A thermoelectric generator (TEG) is a semiconductor-based device that can exhibit a flow of electric current through the external circuit if the sides of the TEG are subjected to a temperature difference caused by a heat source. The terminal voltage and the TEG’s internal resistance are altered depending on the temperature difference. Therefore, a suitable power electronic converter with a maximum power point tracking (MPPT) feature is required to harvest maximum power from the TEG and store the harvested energy in a battery-based energy storage system. This paper investigates a novel energy harvesting methodology from TEG using a series compensated buck-boost converter (SCBBC). MPPT has also been implemented using a sliding mode controller (SMC). A mathematical model of a TEG source has been developed in MATLAB-Simulink and tested with generic boost converter (GBC) and SCBBC for their dynamic performances during battery charging. The efficiency of conversion is found to be higher for SCBBC, at 97.87%. An experimental prototype has been developed with SCBBC and tested for two configurations, viz high voltage and low current configuration. The former configuration exhibits an efficiency of 86.3%, while the latter has an efficiency of 83%. The results indicate that SCBBC, along with SMC, opens up new efficient prospects for harvesting waste heat energy using TEGs. [ABSTRACT FROM AUTHOR]

In this paper, we propose a low-jitter reference-less clock and data recovery (CDR) circuit with a speed range of 9.8–12.5 Gb/s. The proposed CDR uses a multi-stage half-rate bang-bang phase detector (ML-HR-BBPD) to maximize the quantization of the phase difference. In addition, a unit interval adjuster (UIA) is added to the CDR circuit. So that the circuit can minimize the phase detector's phase error before the output clock frequency is locked. Finally, the loop filter (LF) is improved to realize the coarse and fine adjustment of the phase error over a wide range of phase differences. The CDR circuit's total power consumption is reduced by using a half-rate phase detector. The CDR circuit was fabricated in TSMC 40 nm CMOS process. The measured results are obtained in the proposed CDR circuit at a data rate of 12.5 Gb/s. With a pseudo-random bit sequence (PRBS) of 2 3 1 − 1 , the measured result shows that the bit error rate (BER) is < 1 0 − 1 2 , and the root mean square jitter recovered in the output is 0.302 p s rms . The circuit's jitter tolerance (JTOL) is 0.46 UIpp, and its total power consumption is 74.8 mW with a 5.98 pJ/bit energy efficiency. [ABSTRACT FROM AUTHOR]

In the current research on data query for two-tiered WSN, the privacy-preservation range query is one of the hotspots. However, there are some problems in the existing researches in two-tiered wireless sensor networks such as high computational and communication costs for security comparison items and high energy consumption of sensing nodes. In this paper, a privacy-preservation range query protocol based on the integration reversal 0-1 encoding with Bloom filter is researched and designed. In the sensing data submission stage, the optimized reversal 0-1 encoding, HMAC algorithm, AES encryption algorithm and variable-length Bloom filter are used for generating the maximum–minimum comparison encoding and constructing a shorter verification index chain to reduce computational and communication costs of sensing nodes; in the private data range query stage, the base station uses the HMAC algorithm to convert the plaintext query range into the ciphertext query range and sends it to the storage node. In the storage node, the bitmap encoding information of the verification index chain is calculated with the comparison rule of the reversal 0-1 encoding and it is returned to the base station together with the verification index chain and the data ciphertext that compliance with the query rule; in the data integrity verification stage, the integrity of the query results using the verification index chain and bitmap encoding is verified at the base station. In the experimental section, the Cortex-M4 development board equipped with the Alios-Things operating system as sensing node and the Cortex-A9 development board equipped with the Linux operating system as storage node are implemented in this protocol, which is compared with the existing protocols in three aspects: the number of data collected in each cycle, the length of data and the number of data dimensions. The experimental results show that the energy consumption of this protocol is lower under the same experimental environment. [ABSTRACT FROM AUTHOR]

This paper presents a modified energy-efficient Dual Mode Transmission Gate Diffusion Input (DMTGDI) design and is termed as M-DMTGDI. A contention issue in dynamic mode operation of existing DMTGDI design and DMPL design is identified and illustrated through mathematical formulation and simulations. To resolve this concern, the pre-charge/pre-discharge transistor in existing DMTGDI design is replaced by dual mode inverter in the proposal. The functional verification and performance comparison of NAND, NOR, XOR gates and 1-bit full adder based on proposed M-DMTGDI is carried out using 90 nm BSIM4 model card for bulk CMOS using Symica DE tool. The performance of the circuits is evaluated in terms of power, delay and Power Delay Product (PDP) in both static and dynamic modes. The variation of PDP with the ratio of the time the circuit is designed to run in dynamic mode against static mode is also investigated to analyze the energy efficiency of the M-DMTGDI design. The proposed approach offers maximum PDP reduction of 33.52%, 99.39% and 96.61% for 2-input gates as compared to their footed DML, DMPL and DMTGDI counterparts, respectively. The reduction in PDP is quite significant in 1-bit full adder circuit where the corresponding values are 94.18%, 99.41% and 99.79%, respectively. [ABSTRACT FROM AUTHOR]

Memristors can be used to build nonvolatile memory systems with in-memory computing (IMC) capabilities. A number of prior works demonstrate the design of an IMC-capable memory macro using a memristor crossbar. However, read disturbance limits the use of such memory systems built using a 0-transistor, 1-RRAM (0T1R) structure that suffers from the sneak path problem. In this paper, we introduce a scheme for both memory and logic operations using the 1-transistor, 1-RRAM (1T1R) memristor crossbar, which effectively mitigates the read disturbance problem. The memory array is designed using nMOS transistors and the VTEAM memristor model. The peripheral circuitry like decoders, voltage multiplexers, and sense amplifiers is designed using a 45 nm CMOS technology node. We introduce a mapping technique to realize arbitrary logic functions using Majority (MAJ) gate operations in the 1T1R crossbar. Through extensive experimentation on benchmark functions, it has been found that the proposed mapping method gives an improvement of 65% or more in terms of the number of time steps required, and 59% or more in terms of energy consumption as compared to some of the recent methods. [ABSTRACT FROM AUTHOR]

This paper presents the adiabatic logic called 2 N – N –2 P , which can operate with less number of transistors and high energy efficiency than the existing circuit styles. It is a dual rail logic operated by four-phase power clock (PC). The 2 N – N –2 P adiabatic logic is capable of operating through a wide range of frequency from 100 MHz to 1 GHz. Relentless scaling of MOSFETs towards lower technology nodes results in short channel effects in addition to increasing higher leakage current issues. In this scenario, FinFET advantageously replaces MOSFET with its unique features of the elimination of the short channel effects encountered by the MOSFETs with its gate structure that wraps around the channel completely. It incurs that the lower energy consumption and the feasibility of designing energy recovery circuits using FinFETs are analyzed in this paper. Comparatively, the energy efficiency of FinFET-based 2 N – N –2 P against the 2 N 2 N 2 P and Positive Feedback Adiabatic Logic (PFAL) are analyzed. Simulation results also validate the robustness and efficiency of 2 N – N –2 P adiabatic logic circuit under process parameter variations of FinFET technology. Complex adiabatic adders and multipliers taken as bench mark circuits have been designed using 32-nm FinFET technology node and the results validate the enhanced energy efficiency characteristics of 2 N – N 2 P over 2 N 2 N 2 P and PFAL designs. [ABSTRACT FROM AUTHOR]

This paper proposes the hybrid approach for increasing the profit of prosumers and reducing the energy cost of the residents. The hybrid method is the combination of chaotic maps and the Henry gas solubility optimization algorithm (HGSO), hence it is called chaotic Henry gas solubility optimization (CHGSO). The proposed approach is the community-based microgrid that incorporates energy storage systems (ESS), electric vehicles (EVs) and photovoltaics (PV). Both ESS and EV are conserved as alternative sources of energy. The stored EV energy is used as a power source for homes and the grid by utilizing the Grid-to-Vehicle (G2V) and Vehicle-to-Grid (V2G) modes. The power flow of EV/ESS is controlled depending on the rate of charging and discharging. Here, the battery degradation cost is considered. The proposed approach solves the optimization problems, like battery degradation of EV/ESS, regulation of charge/discharge and provides optimal economic benefits. The proposed approach increases the prosumer profit through encouraging EV energy transactions through incentive-based pricing. Finally, the CHGSO method is performed in MATLAB and is compared with existing methods. From the simulation analysis, it can be concluded that the cost of CHGSO method is less and the prosumer participation has increased. [ABSTRACT FROM AUTHOR]

There are cases in energy supply applications with low-power batteries, where the power required by the load is larger than the supply maximum deliverable power. Using a capacitor to create a high instantaneous power for the load was investigated as a useful solution. To increase the charging efficiency, a stepwise method for charging the capacitor was employed. This paper presents a new pulsed power supply approach in which the charging process is resumed after high instantaneous power delivery. Through this, the loss of residual energy in the capacitor was decreased and load turn-on speed and energy efficiency were significantly improved. The proposed structure consists of a buck converter that charges the capacitor using inductor current. A pulse frequency modulation (PFM) technique was used to generate the necessary signals for the buck converter switches, which resulted in controlling the inductor current. The proposed circuit was designed and simulated in a 0.18 μ m CMOS technology. It was shown that the designed CMOS circuit could reach a peak energy efficiency of 93.2% with a sleep period of 1.05 ms when the load consumes 7.06 μ J of energy. [ABSTRACT FROM AUTHOR]

An efficient method primarily depending on nonisolated quasi Z-source (QZS) novel multilevel inverter (NIQZS-NMLI) topology to interconnect photovoltaic (PV) system is proposed in this paper. The proposed hybrid system is the combination of improved chameleon swarm algorithm (ICSA) and recurrent perceptron neural network (RPNN), hence it is named as ICSA–RPNN. Usually, the interface among the PV DC supply, the load is achieved through an NIQZS-NMLI topology. Here, the NIQZS-NMLI topology modeling design is increased with the new storage device to supply the largest amount of power from the PV power production system. The number of switches and full harmonic distortion of the machine are reduced through the NMLI topology, and it is used to achieve better upgrading capability, and reduce the voltage pressure on the entire active switching device has a better modulation index. At first, the objective function is described primarily depending on its controller parameters and control voltages, current, power, and modulation code. These parameters are useful to the inputs of the proposed ICSA-RPNN approach. The ICSA-RPNN methodology enhanced the voltage profile, reducing power distribution, power oscillations simultaneously distributing power to the load. The modulation load is controlled by proposed artificial intelligence (AI) mainly depends on the NIQZS-NMLI topography. In addition, the ICSA-RPNN methodology reduces the injected power, controls the voltage, current and frequency conditions of the DC hyperlink. The ICSA-RPNN approach is performed at MATLAB/Simulink site and the general performance of the output is compared to the existing systems for different load conditions. [ABSTRACT FROM AUTHOR]

In this paper, a low-cost rectenna based on an antipodal Vivaldi antenna (AVA) with elliptical slots (AVA-ES) is developed and analyzed. The design of AVA-ES, when compared to a reference AVA, presents significant improvements in directivity and gain (58% at 2.45 GHz for both), evidencing its advantages for using in rectennas. The proposed rectenna prototype presents satisfactory results at 2.45 GHz, such as conversion efficiency for low-power input levels (27% at − 10 dBm) and maximum output voltage (550 mV), that supports its use for radio-frequency energy harvesting (RFEH). [ABSTRACT FROM AUTHOR]

This paper presents two novel current-mode Full Adders based on Carbon Nanotube FET (CNFET). They comprise of three main parts: current-to-voltage converter, threshold detector and voltage-to-current converter. While other designs in the literature use either inverter or current source for detecting threshold, the new designs are based on a heuristic usage of an Ultra Low-Power Diode (ULPD) as voltage regulator. The use of diode does not lengthen the critical path and thereby ensuring high-speed operation. It does not increase power consumption significantly either. Simulation results by HSPICE and 32nm CNFET technology file demonstrate at least 19% higher performance in terms of energy consumption for the second proposed Full Adder compared to other traditional and state-of-the-art current-mode and mixed-mode designs. [ABSTRACT FROM AUTHOR]

In this paper, we propose a system-level optimization approach for mixed-criticality distributed real-time systems with safety and energy considerations. We firstly depict a mixed-criticality distributed task model for real-time applications, in which the safety of the system is influenced by dynamic voltage and frequency scaling (DVFS). Due to the huge complexity of solving the problem optimally, a heuristic algorithm is proposed to approach the system-level optimization through a quasi-static scheduling strategy. The experiments demonstrate the efficiency of the proposed approach, which can obtain energy consumption while guaranteeing the system safety requirements. [ABSTRACT FROM AUTHOR]

Given the difficulties in measuring the effective wind speed of wind turbine during the maximum power point tracking (MPPT) process and the unknown nature of the system, this paper proposes a neural network super-twisted sliding mode control (NNST-SMC) method with echo state network (ESN) wind speed estimation. The rotor speed and electromagnetic power are taken as ESN inputs, and the effective wind speed is estimated through the inverse model of wind turbine dynamics. The super-twisted algorithm (STA) can effectively improve the chattering problem of the traditional sliding mode control (SMC) system. The RBF neural network is introduced to compensate for disturbance and uncertainty characteristics of the wind turbine. Results show that compared with the neural network first-order sliding mode control (NNSMC) and super-twisted sliding mode control (ST-SMC), the proposed method can improve the efficiency of wind energy utilization. [ABSTRACT FROM AUTHOR]

The increasingly complicated and versatile convolutional neural networks (CNNs) models bring challenges to hardware acceleration in terms of performance, energy efficiency and flexibility. This paper proposes a reconfigurable neural accelerator (RNA) for flexible and efficient CNN acceleration. To provide hardware flexibility, RNA employs dynamically reconfigurable computing framework to rapidly configure data path between processing elements (PE) at run-time, as well as an interlaced data access mechanism for multi-bank RAM. To achieve high energy efficiency, three optimization mechanisms, including image row broadcasting dataflow (IRBD), tile-by-tile computing (TTC), and zero detection technology (ZDT), are dedicatedly designed for RNA to exploit data reuse and decrease memory bandwidth requirement, which is the key to improving performance and saving power consumption. To save hardware overhead, an online dynamic adaptive data truncation (DADT) mechanism is designed to compensate accuracy loss of multiplication results so that the computational precision in RNA can be reduced from 16-bit to 8-bit, which contributes to reducing the area of data path. The RNA architecture is implemented on Xilinx XC7Z100 FPGA and works at 250 MHz. Experimental results show that the performance of running LeNet, AlexNet and VGG are 500 GOPS, 598 GOPS and 660 GOPS, respectively. Compared to previous FPGA-based designs, RNA achieves 1. 5 × − 4. 3 × performance speedup and 7. 6 × − 8. 4 × improvements on energy efficiency. [ABSTRACT FROM AUTHOR]

This paper proposes a deduplication-based mixed page strategy, called DM-Pages, to improve the energy efficiency of disk storage systems and the cache performance. DM-Pages strives to improve the cache hit rate, simultaneously reduce the number of power-state transitions of a disk storage system and keep it in a low-power state as long as possible. DM-Pages deploys three innovative techniques. It adjusts the size of huge pages dynamically to maximize the cache hit rate. Meantime, content-aware deduplication is applied to eliminate redundant cache pages, targeting to enhance cache utilization. In addition, DM-Pages incorporates a mixed page mechanism into disk energy management to save energy. Our experimental results show that DM-Pages significantly improves the energy efficiency of disk storage systems and achieves a high cache hit rate. In particular, compared with traditional disk storage systems, DM-Pages conserves 6.59 times energy and improves the cache hit rate up to 3.36 times. [ABSTRACT FROM AUTHOR]

The crucial role played by digital multipliers in VLSI system design makes it indispensable to study the PPA cards of digital multiplier architectures before tailoring multiplier architecture into such systems. Therefore, in this work, we present a detailed investigation and analysis of PPA cards of popular digital multiplier architectures, for various wordlengths. Each multiplier has been implemented on Artix-7 FPGA xc7a200tfbg676-2 and analyzed using Xilinx Vivado Design Suite 2019.2. A major contribution in this paper is the study of energy profiles of the architectures, not focused on in the earlier literature. This study compares their device utilization, timing parameters, power consumption, and energy profiles. Results indicate that Dadda Tree Multiplier and Wallace Tree Multiplier (460 slices and 557 slices, respectively, for N = 3 2 bits) are undoubtedly the least slices consuming fast multipliers, but their power consumption and energy density are high as well. For 32-bit implementation, Vedic Multiplier consumes 48.9% lower power than Dadda Tree Multiplier, while the latter occupies 30.42% lesser slices. The speed of the Vedic Multiplier is in close proximity with the tree multipliers. The energy density of Vedic Multiplier (0.3 nJ/slice) is much lower than that of Dadda Tree Multiplier (0.77 nJ/slice). [ABSTRACT FROM AUTHOR]

Leakage energy has become an increasingly large fraction of total energy consumption, making it important to reduce leakage energy for improving the overall energy efficiency for embedded processors. In this paper, we explore how to reduce the cache leakage energy efficiently in a hybrid Scratch-Pad Memory (SPM) and cache architecture. Different from stand-alone cache, since the frequently used data may be allocated to the SPM for rapid retrieval in the hybrid architecture, the access frequency to the cache is reduced. It is possible to place the cache lines of the hybrid SPM-cache into the low power mode more aggressively than traditional leakage management for regular caches, which can reduce more leakage energy without significant performance degradation. Also, we propose a Hybrid Drowsy-Gated VDD (HDG) technique, which can adaptively exploit both short and long idle intervals of cache accesses to minimize leakage energy with insignificant performance overhead. In addition, we discussed the impact of cache size on the idle intervals of accesses, which will affect the efficiency of leakage management methods that exploit the idle intervals to reduce leakage energy. [ABSTRACT FROM AUTHOR]

An exhaustive analysis of a four-wing chaotic system is presented in this paper. It is proved that the evolution range of some variables can be modulated easily by one coefficient of a cross product term. An amplitude-adjustable chaotic circuit is designed, which shows a good agreement with the theoretical analysis. Also, in this paper a microcontroller-based random number generator (RNG) was designed with a nonlinear four-wing chaotic system. RNG studies of the current time have been usually carried out with complicated structures that are costly and difficult to use in real time implementations and that require so much energy consumption. On the other hand, in this paper, as opposed to the disadvantages mentioned here, a microcontroller-based RNG was designed with a four-wing chaotic system (also discussed in the paper) and this was introduced to literature. Microcontroller-based random numbers that passed randomness tests will be available for use in many fields in real life, particularly in encryption. [ABSTRACT FROM AUTHOR]

Reversible circuit is of interest due to the characteristics of low energy consumption. This paper proposes a new scheme for synthesizing fault tolerant reversible circuits. A two-step method is put forward to convert an irreversible function into a parity-preserving reversible circuit. By introducing model checking for linear temporal logic, we construct a finite state machine to synthesize small reversible gates from elementary 1-qubit and 2-qubit gates, which is more automatic than the methods proposed previously. Constrains are increased so as to reduce the synthesis time in the two step method. The parity-preserving gate constructed by the two-step method has characteristics of low quantum cost because the quantum representation obtained from the counterexample for a given function in each step has the minimum quantum cost. In order to further reduce the quantum cost and decrease the synthesis time, the semi parity-preserving gates are put forward for the first time. These gates are parity-preserving when the auxiliary input is set to 0 and opposite parity when 1. Maintaining good robustness of the system in performing specific function, semi parity-preserving gate is conducive to detecting the stuck-at fault and partial gate fault in reversible circuits. The innovation of this paper is introducing the formal method to synthesis small fault tolerant gate, so as to construct the circuit with robust (semi) parity-preserving gates. [ABSTRACT FROM AUTHOR]

In this paper, a new algorithm is proposed for computing the node-disjoint optimal transmission energy consumption route for coded cooperative mobile IoT networks. Inspired by the potential benefits user cooperation can provide, we incorporate user cooperation to the mobile ad-hoc multi-hop IoT networks. Our results include a novel ant colony system-based node-disjoint energy-efficient routing algorithm. Ant colony system can approximate the optimal route by local information and is thus very suitable for mobile IoT network environment. In particular, ant algorithm makes history-sensitive choice and thus can significantly outperform the greedy algorithm. In addition, it can efficiently handle the case of multiple sources and multiple destinations. For a large IoT network, we investigate the multi-scale ant colony system and when compared to Dijkstra algorithm, such an algorithm usually shortens the runtime by a factor of several hundred. [ABSTRACT FROM AUTHOR]

In this paper, an offline bandwidth and frequency calibration method for an on–off LC oscillator-based ultra-wideband impulse radio (UWB-IR) transmitter is presented. Implemented in 0.18- μ m CMOS, the offline calibration circuits consume very little power. This allows the transmitter to consume an ultra-low average power of 319 μ W over 3–5 GHz at 2 Mbps. The calibration is critical to ensure the FCC spectral mask compliance despite the process–voltage–temperature (PVT) variations. The transmitter can deliver a large differential output swing of 1.8–3 V to a 100- Ω load with minimal power efficiency of 7% at different data rates (2–30 Mbps). It is suitable for WPAN application with localization and positioning capabilities. [ABSTRACT FROM AUTHOR]

A novel multiband impulse radio ultra-wideband (MB-IR-UWB) transmitter with an energy-efficient and low-complexity pulse generator design technique compliant with the IEEE 802.15.4a standard is investigated in this paper. This transmitter is made up of a new differential narrow triangular pulse generator, a new multiband voltage-controlled oscillator (VCO), an active mixer and a variable-gain power amplifier (PA). It operates at 14 UWB bands and generates an output signal with the duration of 3 ns, more than 500 MHz of channel bandwidth and more than 20 dB of sidelobe suppression, while achieving an average energy efficiency of 51.36 pJ/pulse from 1.4-V supply. Improving spectral flexibility and worldwide compliance is the major contribution brought by this paper to make this circuit as a multifunction wireless device well suited for low-cost, low-power multiband applications. [ABSTRACT FROM AUTHOR]

This paper considers the design of robust logarithmic μ -law companding quantizers for the use in analog-to-digital converters (ADCs) in communication system receivers. The quantizers are designed for signals with the Gaussian distribution, since signals at the receivers of communication systems can be very well modeled by this type of distribution. Furthermore, linearization of the logarithmic μ -law companding function is performed to simplify hardware implementation of the quantizers. In order to reduce energy consumption, low-resolution quantizers are considered (up to 5 bits per sample). The main advantage of these quantizers is high robustness — they can provide approximately constant SNR in a wide range of signal power (this is very important since the signal power at receivers can vary in wide range, due to fading and other transmission effects). Using the logarithmic μ -law companding quantizers there is no need for using automatic gain control (AGC), which reduces the implementation complexity and increases the speed of the ADCs due to the absence of AGC delay. Numerical results show that the proposed model achieves good performances, better than a uniform quantizer, especially in a wide range of signal power. The proposed low-bit ADCs can be used in MIMO and 5G massive MIMO systems, where due to very high operating frequencies and a large number of receiving channels (and consequently a large number of ADCs), the reduction of ADC complexity and energy consumption becomes a significant goal. [ABSTRACT FROM AUTHOR]

The cache system dissipates a significant amount of energy compared to the other memory components. This will be intensified if a cache is designed with a set-associative structure to improve the system performance because the parallel accesses to the entries of a set for tag comparisons lead to even more energy consumption. In this paper, a novel method is proposed as a combination of a counting Bloom filter and partial tags to mitigate the energy consumption of set-associative caches. This new hybrid method noticeably decreases the cache energy consumption especially in highly-associative instruction caches. In fact, it uses an enhanced counting Bloom filter to predict cache misses with a high accuracy as well as partial tags to decrease the overall cache size. This way, unnecessary tag comparisons can be prevented and therefore, the cache energy consumption is considerably reduced. Based on the simulation results, the proposed method provides the energy reduction from 22% to 31% for 4-way–32-way set-associative L1 caches bigger than 16 kB running the MiBench programs. The improvements are attained with a negligible system performance degradation compared to the traditional cache system. [ABSTRACT FROM AUTHOR]

The congestion caused by ramp overflow has an essential impact on the energy consumption of autonomous vehicles. It is urgent to solve the energy waste of ramp overflow on connected and autonomous vehicles and improve the energy utilization rate. Aiming at the traffic congestion caused by ramp overflow, this paper obtains the data of autonomous vehicles and traffic flow based on vehicle road cooperative perception, analyzes the impact mechanism of vehicle energy consumption, and summarizes the energy consumption modes of autonomous vehicles into three categories. Second, an energy consumption evaluation framework is proposed based on the CSANS strategy. This strategy can make up for the deficiency of constructing neighborhoods within European distance, find important influencing variables on connected and autonomous vehicles' energy consumption, and accurately capture the manifold characteristics of energy consumption data. Finally, flow control is carried out from the macro perspective of traffic engineering to optimize ramp overflow's impact on autonomous vehicles' energy consumption. Through multiple groups of experiments, it has been found that it can effectively reduce the energy consumption of autonomous vehicles. [ABSTRACT FROM AUTHOR]

An Internet of Things (IoT) device that can automatically measure water consumption can help prevent excessive water usage or leaks. However, automating too many residences or condominiums with multiple IoT devices can lead to extra energy consumption and more network congestion. We propose controlling the energy consumption of an IoT water consumption management system by dynamically controlling its duty cycle. By analyzing the energy consumption of the developed prototype and its duty cycle variation, we calculated how much energy could be saved by controlling the antenna and the water flow sensor used in the IoT device. While controlling the antenna offered some energy savings, having some way to cut down on the water flow sensor's consumption can have a dramatic impact on the overall IoT energy consumption or its battery longevity. Our results showed that we could get up to 69% extra energy savings compared to just putting the antenna in sleep mode. There is an observable trade-off in saving so much energy, as we can also see that water reading error rates go up alongside the extra energy savings. [ABSTRACT FROM AUTHOR]

In the modern Block-chain and Artificial Intelligence era, energy efficiency has become one of the most important design concerns. Approximate computing is a new and an evolving field promising to provide energy-accuracy trade-off. Several applications are tolerant to small degradation in results, and hence tasks like image and video processing are candidates to benefit from Approximate Computing. In this paper, we propose a new design approach for designing approximate adders and further optimize the accuracy and cost metrics. Our approach is based on minimizing the errors while cascading more than one 1-bit adder. We insert | error | = 1 on specific locations to achieve a reasonable circuit minimization and reduce the error × count gate cost. We compare our design with exact adder and relevant state-of-the-art approximate adders. Through analysis and simulations, we show that our approach provides higher accuracy and far better performance compared with other designs. The proposed double bit approximate adder provides more than 25% savings in gate count compared with the exact adder, has a mean absolute error of 0.25 which is lowest among all the reference approximate adders and reduces the power-delay product by more than 60% compared to the exact adder. When employed for image filtering, the proposed design provides a PSNR avg of 96%, a SNR avg of 95% and a SSIM avg of 91% relative to the actual results, while the second best approximate adder only achieves 64%, 54% and 71% of these image quality metrics, respectively. [ABSTRACT FROM AUTHOR]

A 12-bit 500-MS/s current steering digital-to-analog converter (DAC) for high-speed power line communication (PLC) modems is presented in this paper. The performance of current steering DAC is limited by the current cell mismatches and glitch problems caused by switching timing errors. In this paper, the current cell design procedure is presented to minimize random mismatches. Then, a new data-weighted averaging (DWA) technique with fewer glitches and low hardware complexity is proposed to compensate for the gradient mismatch. Spurious-free dynamic range (SFDR) improvement and low complexity are effectively achieved by employing both a row-column structure and a (CSA) structure as the floor plan of the proposed DAC. The proposed DAC is implemented in a standard 0.18-m CMOS process with an active area of 2.445mm2, which achieves a differential non linearity (DNL) of 0.25LSB and an integral non-linearity (INL) of 0.19LSB. Additionally, the SFDR increases by 13.2dB (on average) when employing the proposed DWA technique. The total power consumption of the proposed DAC is 176mW from a 1.8-V supply voltage. [ABSTRACT FROM AUTHOR]

This paper presents a novel high-speed and highly energy-efficient double-tail dynamic comparator. In order to achieve high speed, a hybrid design style is adopted for pre-amplifier stage and a new design is proposed for latch stage, which enhances the speed and reduces the effect of kickback noise. The latch stage delay and energy efficiency of the proposed design are optimized with respect to the width of each transistor. To verify the outcomes, the proposed comparator is simulated using 45 nm and 180 nm CMOS process. Monte Carlo simulation is also done for each parameter. The 45 nm result shows that the comparator has the total delay as low as 104.3 ps and consumes only 0.288 fJ of energy per conversion from a 0.8 V supply. The mean value of input voltage error due to kickback noise is found as 306 nV. [ABSTRACT FROM AUTHOR]

With the rapid development of embedded systems, users and services have been greatly facilitated while also experiencing security threats as a result of cyber-attacks and system vulnerabilities. Currently, the real-time embedded system (RTES) focus is to deal with these security issues. In this paper, we introduce a short review of security-aware techniques for RTES. We mainly discuss two common approaches to improve the security of RTESs. The first approach is achieved by exploring specific attacks. The second approach is realized by deploying security-guaranteed services. However, improving the security of embedded systems may cause excessive energy consumption at the same time. Therefore, we investigate the secure and energy-aware RTESs on a wide range of research. In addition, we study a number of common applications used in secure RETSs. This paper stands for providing awareness and better understanding of the current RTES research status as well as technical theory behind it. Hence, the RTES security issues are resolved. [ABSTRACT FROM AUTHOR]

As power consumption is one of the major issues in biomedical implantable devices, in this paper, a novel quantization method is proposed for successive approximation register (SAR) analog-to-digital converters (ADCs) which can save 80% power consumption in contrast to conventional structure for electroencephalogram (EEG) signal recording systems. According to the characteristics of neural signals, the principle of the proposed power saving technique was inspired such that only the difference between current input sample and the previous one is quantized, using a power efficient SAR ADC with fewer resolutions. To verify the proposed quantization scheme, the ADC is systematically modeled in Matlab and designed and simulated in circuit level using 0.18 μ m CMOS technology. When applied to neural signal acquisition, spice simulations show that at sampling rate of 25 kS/s, the proposed 8-bit ADC consumes 260 nW of power from 1.8 V supply voltage while achieving 7.1 effective number of bits. [ABSTRACT FROM AUTHOR]

Quantum-dot Cellular Automata (QCA) as a nanoscale transistor-less device technology offers distinguishing advantages over the limitations of CMOS circuits. This nanoelectronic is based on the mapping of binary logic in the two excess electrons configuration within a four-dot cell. In this paper, we propose a new ultra-low energy and low-complexity two-input XOR gate which can be employed as a basic component in designing a wide range of QCA logical circuits. For performance evaluation of the presented design in a large array of QCA structures, even parity generator circuit with different lengths up to 32 bits as well as LFSR circuit are designed and analyzed as instances of logical circuits. The simulation results reveal that our proposed designs have significant improvements in contrast to counterparts from hardware implementation requirements and energy consumption aspects. QCADesigner tool is utilized to evaluate functional correctness of the proposed circuits and power dissipation is evaluated using QCAPro simulator as an accurate power estimator tool. [ABSTRACT FROM AUTHOR]

Reversible computations have attracted a lot of attention in recent years due to the ability to reduce energy dissipation that is needed in nanocircuits. The main purpose of designing reversible circuits is to reduce the energy consumption that occurs due to the loss of input bits in irreversible circuits. In this paper, we initially proposed a new 5 × 5 reversible block and then its quantum realization is given using the Miller et al. method. In the following, an effective reversible design of D flip-flop is introduced using the proposed reversible block. Finally, four types of reversible shift register including serial-in to parallel-out (SIPO), parallel-in to parallel-out (PIPO), parallel-in to serial-out (PISO) and shift counter are proposed using the proposed reversible flip-flop. The evaluation results show that the proposed circuits are superior compared to the existing designs in terms of quantum cost (QC). [ABSTRACT FROM AUTHOR]

This paper presents a low-power low-noise instrumentation amplifier (IA) intended for biopotential signal recordings. The IA is designed based on a capacitively-coupled topology, which achieves wide input common-mode range, high common-mode rejection ratio (CMRR) and low power consumption. To reduce low-frequency noise and output ripple at the same time, a combination of chopping and ping-pong auto-zeroing techniques, which is normally used in current-feedback IAs, is introduced for the capacitively-coupled topology in this paper. An intrinsic adverse effect of the proposed structure which causes additional ripple is analyzed. The DC electrode offset voltage is suppressed and the input impedance is boosted through feedback techniques. An improved switched-capacitor common mode feedback (SC CMFB) circuit is also presented. Test results show that the IA achieves an equivalent input-referred noise power spectrum density of 60 nV/sqrtHz and a noise efficiency factor (NEF) of 5.58. The bandwidth is 0.5 Hz to 10 kHz, covering most biopotential recording applications. The IA was implemented in 0.18-μm CMOS process. It occupies 0.27 mm2 core area and consumes 3.6 μA from a 1 V supply. [ABSTRACT FROM AUTHOR]

Initially introduced as special-purpose accelerators for graphics applications, graphics processing units (GPUs) have now emerged as general purpose computing platforms for a wide range of applications. To address the requirements of these applications, modern GPUs include sizable hardware-managed caches. However, several factors, such as unique architecture of GPU, rise of CPU-GPU heterogeneous computing, etc., demand effective management of caches to achieve high performance and energy efficiency. Recently, several techniques have been proposed for this purpose. In this paper, we survey several architectural and system-level techniques proposed for managing and leveraging GPU caches. We also discuss the importance and challenges of cache management in GPUs. The aim of this paper is to provide the readers insights into cache management techniques for GPUs and motivate them to propose even better techniques for leveraging the full potential of caches in the GPUs of tomorrow. [ABSTRACT FROM AUTHOR]

Scratch-Pad Memories (SPMs) have been increasingly used in real-time and embedded systems. However, it is still unknown and challenging to reduce the worst-case execution time (WCET) for hybrid SPM-cache architecture, where an SPM and a cache memory are placed on-chip in parallel to cooperatively improve performance and/or energy efficiency. In this paper, we study four SPM allocation strategies to reduce the WCET for hybrid SPM-caches with different complexities. These algorithms differ by whether or not they can cooperate with the cache or be aware of the WCET. Our evaluation shows that the cache-aware and WCET-oriented SPM allocation can minimize the WCET for real-time benchmarks with little or even positive impact on the average-case execution time (ACET). [ABSTRACT FROM AUTHOR]

COrdinate Rotation DIgital Computer (CORDIC) is commonly utilized for the computation of cosine/sine i.e., the trigonometric functions, singular value decomposition, in digital signal processing (especially in image/video processing), etc. This paper introduces an energy efficient quality tunable CORDIC architecture that computes the cosine/sine values of any required angle in real-time, and is thus well suited for real time DSP applications, especially for image or video processing applications. The proposed architecture reduces the latency and overcomes data dependency by simultaneously performing all the five iterations, that may vary depending upon the desired energy efficiency. The novelty of this architecture is that, desired quality can be achieved by selecting one out of the available three modes. In order to assess the efficacy of the suggested architecture, some benchmark images are processed using the Discrete Cosine Transform (DCT) coefficients obtained via the proposed design. Energy saving is achieved at the cost of slight acceptable degradation in the output image quality. Further, the simulation results show that the proposed architecture is 92.3%, 2.8% and 49.08% more energy efficient than the existing basic, scale-free and lookahead CORDIC architectures, respectively. [ABSTRACT FROM AUTHOR]

Tunnel field-effect transistors (TFETs) as low voltage device options have attracted recent attention for energy efficient circuit designs with CMOS technology scaling. This paper presents the circuit and architectural co-design approach for designing reliable and energy efficient architectures (adder cells) for new computing platforms at supply voltages. At circuit level TFET-based 28-transistor static logic design (28T) and 24-transistor transmission gate logic design (24T) have been explored. At architectural level, multiplexer (MUX)-based 22-transistor full adder design (22T) is proposed. Performance of TFET-based architectures have also been benchmarked with 20nm double gate Si FinFET technology. It has been seen that with FinFET technology 24T design is not effective in terms of energy efficiency and reliability (due to the large leakage currents in transmission gate logic topology). 28T design is the best in reliability perspective (in terms of reduced over shoots, full logic swing and reduced glitch duration etc.) and 22T design to be energy efficient option. It has been demonstrated in this paper that TFET's steep slope characteristics enable the 24T design to have similar reliability characteristics like 28T design and energy efficiency like 22T design. TFET-based 22T design has 91% smaller energy delay product (EDP) and 84.4% less power delay product (PDP) in comparison to the low threshold voltage (LVT) FinFET 22T design at 0.2V VDD. [ABSTRACT FROM AUTHOR]

A novel energy-efficient switching scheme for successive approximation register (SAR) analog-to-digital converters (ADC) is proposed in this paper. The average switching energy of the proposed switching scheme can be reduced by 95.3%, compared with the -based scheme. Moreover, the linearity has been also improved significantly. Employing the proposed switching scheme, a 10-bit 100kS/s SAR ADC is designed in SMIC 0.18-m CMOS process. At a 0.6-V supply, the ADC consumes 43.7nW. Consequently, the figure-of-merit (FOM) is optimized to 0.58fJ/conversion-step. [ABSTRACT FROM AUTHOR]

Wireless Sensor Networks (WSNs) are used for data collection from the surrounding environment using the enormous amount of sensor nodes. Energy saving is the most fundamental challenge of WSNs which primarily depends on the Cluster Head (CH) selection and packet routing strategy. In this paper, we are proposing an Energy Aware Distance-based Cluster Head selection and Routing (EADCR) protocol to extend the lifetime of WSN using the FCM technique, residual energy of the nodes, their relative Euclidean distances from the Base Station (BS) and cluster centroid. Since the nodes consume a considerable amount of energy during the clustering phase, thus to avoid this, here, we are introducing a new clustering approach where the CH selection is now based on the newly proposed fitness function. We are also providing a new strategy for packet routing using the shortest path technique for routing between node and its destination which reduces the energy consumption of the CHs by employing the multi-hop communication. We also save the energy of the nodes using their Euclidean distances among them, from their CH and from BS. The simulation results exhibit that the EADCR enhances the network lifetime as compared to the other similar algorithms, e.g., FCM, REHR, UCRA–GSO and CCA–GWO under different scenarios. It also saves the residual energy of the network and enhances the network coverage. [ABSTRACT FROM AUTHOR]

Consuming energy at the maximal level is a major concern in wireless sensor networks (WSNs). Many researchers focus on reducing and preserving the energy. The duration of active network of WSNs is affected by energy consumption of sensor nodes. For typical applications such as structure monitoring, border surveillance, integrated into the external surface of a pipeline, and clambered along the sustaining structure of a bridge, sensor node energy efficiency is an important issue. The paper proposed an energy-efficient multi-hop routing protocol using hybrid optimization algorithm (E2MR-HOA) for WSNs. The proposed routing protocol consists of two algorithms, i.e., hybrid optimization algorithm. We present modified chemical reaction optimization (MCRO) algorithm to form clusters and select cluster head (CH) among the cluster members. Then the modified bacterial forging search (MBFS) algorithm is used to compute reliable route between source to destination. The proposed E2MR-HOA protocol is evaluated using NS2 simulations. The simulation result shows that the proposed routing protocol provides significant energy efficiency with network lifetime over the existing routing protocols. [ABSTRACT FROM AUTHOR]

This paper presents a reconfigurable architecture for Network-on-Chip (NoC) design based on configuration switches. Reconfiguration is achieved by varying connection pattern between routers, depending on the currently running application. Mapping and reconfiguration strategies have been developed for the proposed architecture. In the mapping phase, cores in the combined application set are mapped to individual routers, minimizing the overall communication cost. In the second phase, for each application, configuration information for the switches (between the routers) are generated to optimize the communication cost further to suit the corresponding application. Exact methods, based on Integer Linear Programming (ILP), have been proposed for both the phases. Since ILP takes a large amount of CPU time, Particle Swarm Optimization (PSO)-based approaches have also been developed. The architecture and mapping strategies have been evaluated against benchmarks, considering communication cost, throughput, latency and network energy before and after reconfiguration. Significant improvements could be achieved via reconfiguration. Compared to the approaches reported in the literature, communication cost, throughput, latency and energy consumption values improve by 23.4%, 4%, 3% and 7%, respectively. These improvements come at a nominal increase in area overhead of 0.07%. [ABSTRACT FROM AUTHOR]