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Cache-Aware SPM Allocation to Reduce Worst-Case Execution Time for Hybrid SPM-Caches.
- Source :
- Journal of Circuits, Systems & Computers; May2018, Vol. 27 Issue 5, p-1, 23p
- Publication Year :
- 2018
-
Abstract
- Scratch-Pad Memories (SPMs) have been increasingly used in real-time and embedded systems. However, it is still unknown and challenging to reduce the worst-case execution time (WCET) for hybrid SPM-cache architecture, where an SPM and a cache memory are placed on-chip in parallel to cooperatively improve performance and/or energy efficiency. In this paper, we study four SPM allocation strategies to reduce the WCET for hybrid SPM-caches with different complexities. These algorithms differ by whether or not they can cooperate with the cache or be aware of the WCET. Our evaluation shows that the cache-aware and WCET-oriented SPM allocation can minimize the WCET for real-time benchmarks with little or even positive impact on the average-case execution time (ACET). [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 02181266
- Volume :
- 27
- Issue :
- 5
- Database :
- Complementary Index
- Journal :
- Journal of Circuits, Systems & Computers
- Publication Type :
- Academic Journal
- Accession number :
- 127813245
- Full Text :
- https://doi.org/10.1142/S0218126618500809