Design and Analysis of an Energy-Efficient High-Speed CMOS Double-Tail Dynamic Comparator with Reduced Kickback Noise Effect.

This paper presents a novel high-speed and highly energy-efficient double-tail dynamic comparator. In order to achieve high speed, a hybrid design style is adopted for pre-amplifier stage and a new design is proposed for latch stage, which enhances the speed and reduces the effect of kickback noise. The latch stage delay and energy efficiency of the proposed design are optimized with respect to the width of each transistor. To verify the outcomes, the proposed comparator is simulated using 45 nm and 180 nm CMOS process. Monte Carlo simulation is also done for each parameter. The 45 nm result shows that the comparator has the total delay as low as 104.3 ps and consumes only 0.288 fJ of energy per conversion from a 0.8 V supply. The mean value of input voltage error due to kickback noise is found as 306 nV. [ABSTRACT FROM AUTHOR]