262 results on '"Manchanda, L."'
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2. Multi-component high- K gate dielectrics for the silicon industry
3. Kinetic smoothening: Growth thickness dependence of the interface width of the Si(001)/SiO2 interface.
4. The nature of intrinsic hole traps in thermal silicon dioxide.
5. Composition-dependent crystallization of alternative gate dielectrics
6. Etching of high-kdielectric Zr1−xAlxOy films in chlorine-containing plasmas
7. Crystallization kinetics in amorphous (Zr[sub 0.62]Al[sub 0.38])O[sub 1.8] thin films
8. High K gate dielectrics for the silicon industry.
9. Si-doped aluminates for high temperature metal-gate CMOS: Zr-Al-Si-O, a novel gate dielectric for low power applications.
10. Comparisons of slow release tramadol 200 mg with placebo in patients undergoing total abdominal hysterectomy
11. High K Dielectrics for CMOS and Flash
12. Gate capacitance attenuation in MOS devices with thin gate dielectrics
13. Thickness dependence of boron penetration through O/sub 2/- and N/sub 2/O-grown gate oxides and its impact on threshold voltage variation
14. Study of Penetrated Boron Concentration through Ultra-Thin Oxynitrided Gate Dielectrics
15. Rapid thermal oxidation of silicon in N2O between 800 and 1200 °C: Incorporated nitrogen and interfacial roughness
16. Growth temperature dependence of the Si(001)/SiO2interface width
17. A new method to fabricate thin oxynitride/oxide gate dielectric for deep submicron devices
18. Fluorine effect on boron diffusion of p/sup +/ gate devices (MOSFETs).
19. Gate quality doped high K films for CMOS beyond 100 nm: 3-10 nm Al/sub 2/O/sub 3/ with low leakage and low interface states.
20. Impact of boron diffusion through O/sub 2/ and N/sub 2/O gate dielectrics on the process margin of dual-poly low power CMOS.
21. The impact of nitrogen profile engineering on ultrathin nitrided oxide films for dual-gate CMOS ULSI.
22. A boron-retarding and high interface quality thin gate dielectric for deep-submicron devices.
23. Hot-Electron Trapping and Generic Reliability of p + Polysilicon/SiO2/Si Structures for Fine-Line CMOS Technology.
24. The Effect of TaSi2/n+ Poly Gate on Hot-Electron Instability of Small Channel MOSFETs.
25. Crystallization kinetics in amorphous (Zr0.62Al0.38)O1.8 thin films.
26. Etching of high-k dielectric Zr1-xAlxOy films in chlorine-containing plasmas.
27. Dielectric breakdown of oxide films in electronic devices.
28. Hole traps in thermal silicon dioxide introduced by chlorine.
29. Inversion layer mobility of MOSFET's fabricated with NMOS Submicrometer technology.
30. A high-performance directly insertable self-aligned ultra-rad-hard and enhanced isolation field-oxide technology for gigahertz silicon NMOS/CMOS VLSI.
31. Lysine-based non-cytotoxic ultrashort self-assembling peptides with antimicrobial activity.
32. Study of thermally oxidized yttrium films on silicon.
33. Anomalous C-V characteristics of implanted poly MOS structure in n/sup +//p/sup +/ dual-gate CMOS technology.
34. A high-performance directly insertable self-aligned ultra-radiation-hard and enhanced isolation field-oxide technology for gigahertz Si-CMOS VLSI.
35. Yttrium oxide/silicon dioxide: a new dielectric structure for VLSI/ULSI circuits.
36. γ—Radiation effects on MOSFET's fabricated with NMOS Submicrometer technology.
37. Growth temperature dependence of the Si(001)/SiO[sub 2] interface width.
38. IVB-7 yttrium oxide/silicon dioxide: A new dielectric structure for VLSI/ULSI
39. Electron Traps in SiO2 Grown in the Presence of Trichloroethylene
40. Gate current in 0.75μm N-channel MOSFETs with doubly diffused drain
41. Erratum: “Electron Traps in SiO2 Grown in the Presence of Trichloroethylene” [J. Electrochem. Soc., 129, 2772 (1982)]
42. The effect of high temperature annealing on the spatial variation of bulk lifetime near the SiSiO2 interface
43. Gate quality doped high K films for CMOS beyond 100 nm: 3-10 nm Al/sub 2/O/sub 3/ with low leakage and low interface states
44. Si-doped aluminates for high temperature metal-gate CMOS: Zr-Al-Si-O, a novel gate dielectric for low power applications
45. High K gate dielectrics for the silicon industry
46. A robust, 1.8 V 250 μW direct-contact 500 dpi fingerprint sensor
47. The impact of nitrogen profile engineering on ultrathin nitrided oxide films for dual-gate CMOS ULSI
48. A symmetric 0.25 μm CMOS technology for low-power, high-performance ASIC applications using 248 nm DUV lithography
49. A Van der Waals plug‐and‐probe approach.
50. Temperature and channel-length dependence of impact ionization in p-channel MOSFETs.
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