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11,233 results on '"Integrated circuits -- Intellectual property"'

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1. Patent Issued for Methods relating to intestinal organ-on-a-chip (USPTO 12104174)

3. From 'Made in China' to 'Created in China': Intellectual Property Rights in the People's Republic of China

4. Patent Issued for Asynchronous ASIC (USPTO 12135580)

6. Researchers Submit Patent Application, 'Integrated Circuit Device Including Peripheral Circuit And Cell Array Structures, And Electronic System Including Same', for Approval (USPTO 20240429187)

8. Patent Application Titled 'Optical Memory Module And Optical Computing System Including The Same' Published Online (USPTO 20240427715)

10. 'Transformer-Based Distributed Multicore Oscillator And Integrated Circuit And Terminal Thereof' in Patent Application Approval Process (USPTO 20240429863)

11. Researchers Submit Patent Application, 'Adaptive Local Throttle Management Of Processing Circuits Based On Detected States In An Integrated Circuit (Ic) Chip', for Approval (USPTO 20240427367)

12. Patent Application Titled 'Throttle Control Circuits For Throttling Activity In Processing Segment Circuits In An Integrated Circuit (Ic) Chip And Related Methods' Published Online (USPTO 20240427368)

13. Patent Application Titled 'Hierarchical Power Estimation And Throttling In A Processor-Based System In An Integrated Circuit (Ic) Chip' Published Online (USPTO 20240427410)

14. Patent Application Titled 'Method Of Forming Photomask, Layout Pattern And System For Patterning Semiconductor Substrate By Using Photomask' Published Online (USPTO 20240427230)

15. Patent Application Titled 'Integrated Circuits (Ic) Chips Including Throttle Request Accumulate Circuits For Controlling Power Consumed In Processing Circuits And Related Methods' Published Online (USPTO 20240427397)

16. Patent Application Titled 'Broadcasting Power Limiting Management Responses In A Processor-Based System In An Integrated Circuit (Ic) Chip' Published Online (USPTO 20240428024)

17. 'Hierarchical Power Estimation And Throttling In A Processor-Based System In An Integrated Circuit (Ic) Chip' in Patent Application Approval Process (USPTO 20240427411)

18. 'Adaptive Local Throttle Management Of Processing Circuits Based On Detected States In An Integrated Circuit (Ic) Chip' in Patent Application Approval Process (USPTO 20240427369)

19. Researchers Submit Patent Application, '8-T Sram Bitcell For Fpga Programming', for Approval (USPTO 20240428848)

20. Patent Issued for Regression neural network for identifying threshold voltages to be used in reads of flash memory devices (USPTO 12175363)

21. Patent Issued for Processing of ethernet packets at a programmable integrated circuit (USPTO 12174782)

22. Patent Issued for Method for detecting reverse engineering on a processor using an instruction pointer and corresponding integrated circuit (USPTO 12174950)

23. Patent Issued for FPGA-based USB 3.0/3.1 control system (USPTO 12174779)

25. Patent Application Titled 'Receivers And Semiconductor Memory Devices Including The Same' Published Online (USPTO 20240430140)

26. Patent Application Titled 'Decision Feedback Equalization In Semiconductor Devices' Published Online (USPTO 20240428822)

27. 'Traffic Management And Control Method And Apparatus, And Device And Readable Storage Medium' in Patent Application Approval Process (USPTO 20240430210)

28. Researchers Submit Patent Application, 'VIRTUALIZATION, VISUALIZATION AND AUTONOMOUS DESIGN & DEVELOPMENT OF OBJECTS', for Approval (USPTO 20240420433)

30. Patent Application Titled 'Integrated Circuit' Published Online (USPTO 20240422793)

31. 'Integrated Circuit Apparatus And Oscillator' in Patent Application Approval Process (USPTO 20240421091)

32. 'Integrated Circuit Devices Including A Backside Power Distribution Network Structure And Methods Of Forming The Same' in Patent Application Approval Process (USPTO 20240421154)

33. 'Computing System And Integrated Circuit Design System Using The Same' in Patent Application Approval Process (USPTO 20240419884)

34. Patent Issued for Seamlessly integrated microcontroller chip (USPTO 12169464)

35. Patent Issued for Method for external devices accessing computer memory (USPTO 12169647)

37. Researchers Submit Patent Application, 'Semiconductor Integrated Circuit Device', for Approval (USPTO 20240421089)

38. Researchers Submit Patent Application, 'Integrated Circuit Workload, Temperature, And/Or Sub-Threshold Leakage Sensor', for Approval (USPTO 20240418770)

39. Researchers Submit Patent Application, 'Semiconductor Device And Method Of Forming The Same', for Approval (USPTO 20240422958)

40. Researchers Submit Patent Application, 'Inverted Gate Cut Region', for Approval (USPTO 20240420959)

41. Researchers Submit Patent Application, 'Integrated Thermal Bridges On Wirebond Assembled Integrated Circuits For Heat Spreading', for Approval (USPTO 20240421092)

43. Patent Issued for Surge protection in semiconductor integrated circuit and semiconductor memory device (USPTO 12170440)

44. Patent Issued for Microprocessor with a time counter for statically dispatching extended instructions (USPTO 12169716)

45. Patent Issued for High voltage MOSFET device with improved breakdown voltage (USPTO 12170329)

46. Patent Application Titled 'Semiconductor Devices With Different Gate Dielectric Thicknesses' Published Online (USPTO 20240421209)

47. Patent Application Titled 'Semiconductor Device And Method Of Forming The Same' Published Online (USPTO 20240421184)

49. 'Semiconductor Package' in Patent Application Approval Process (USPTO 20240421143)

50. 'Recess Poly Esd Diode For Power Mosfet' in Patent Application Approval Process (USPTO 20240421147)

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