Search

We report on inter-chip bidirectional communication and power transfer between two stacked chips. The experimental prototype system components were fabricated in a 0.5-[micro]m silicon-on-sapphire CMOS technology. Bi-directional communication between the two chips is experimentally measured at 1 Hz-15 MHz. The circuits on the floating top chip are powered with capacitively coupled energy using a charge pump. This is the first demonstration of simultaneous nongalvanic power and data transfer between chips in a stack. The potential use in 3-D VLSI is aimed at reducing costs and complexity that are associated with galvanic inter-chip vias in 3-D integration. Index Terms--AC coupling, capacitive coupling, chip-to-chip communication, multichip module, proximity communication, silicon-on-insulator (SOI), silicon-on-sapphire (SOS), three-dimensional (3-D) integration.

We report on an 8-bit successive approximation analog-to-digital converter (SA-ADC) that was designed and fabricated in 0.5-[micro]m silicon on sapphire CMOS technology. The SA-ADC is capable of 32-MHz operation, providing 1.23-MS/s conversion rates, and consumes 800 [micro]W at 3.3-V supply. The lack of substrate parasitic capacitances enables the use of small-area capacitors and reduces the noise coupling to the analog nodes. The circuits employ MOS transistors of different thresholds to optimize the performance and power dissipation of the system. Index Terms--Analog-to-digital converters (ADCs), low power, low voltage, silicon-on-insulator (SOI) silicon-on-sapphire (SOS), successive approximation (SA).

We report on the architecture and experimental characterization of a small-footprint optoelectronic receiver for parallel arrays of optical interconnects. The receiver is designed and fabricated in the 0.5-[micro]m silicon on sapphire CMOS technology. The circuit design exploits the properties of MOS transistors with three different threshold voltages and the insulating substrate to achieve a low-power, high-speed and compact circuit. The design attains a 7-pJ energy per bit transduction cost when operated at 1 Gbit/s data rates. Index Terms--Chip-to-chip communication, optical interconnect, optoelectronic receiver, silicon-on-insulators (SOI) CMOS, silicon on sapphire (SOS) CMOS.

We propose a programmable architecture for a single instruction multiple data image processor that has its foundation on the mathematical framework of a simplicial cellular neural networks. We develop instruction primitives for basic image processing operations and show examples of processing binary and gray scale images. Fabricated in deep submicron CMOS technologies, the complexity of the digital circuits and wiring in each cell is commensurate with pixel level processing. Index Terms--Cellular neural networks (CNNs), CMOS imager sensor, digital pixel, image processing, pixel level processing, vision chips.

Sound localization using energy-aware hardware for sensor networks nodes is a problem with many applications in surveillance and security. In this paper, we evaluate four algorithms for sound localization using signals recorded in a natural environment with an array of commercial off-the-shelf microelectromechanical systems microphones and a specially designed compact acoustic enclosure. We evaluate performance of the algorithms and their hardware complexity which relates directly to energy consumption. Index Terms--Direction of arrival estimation, intelligent sensors, networks.

We examine channel access algorithms and circuits for intra and inter chip communication channels. Classical access techniques such as arbitration, scanning, ALOHA, and priority encoding are compared by assessing throughput, latency, and power consumption. Our results provide guidance in the design of bio-inspired networks of processors, for efficient transmission of information with limited power consumption and reduced latency. Index Terms--Accent topologies, address-event, ALOHA, bioinspired systems, inter-chip communication.

We present results from a radiation dosimeter based on the erasure of floating-gate MOS transistors. Background theory and analysis necessary to describe the operation of the sensor are presented. Index Terms--Dosimetry, floating-gate, radiation effects.

We derive a relationship between quality of data reconstruction, data transmission rate, and integration decay rate for a stochastic transmitter and integrating receiver. This relationship can be used to quantify frame and directly compare the efficiencies of scanned and address-event data representations. We find that high quality reconstruction of stochastic data requires time and dynamic range at the receiver, but a stochastic representation can provide advantages over scanning for some applications. As an example, we provide the design of a simple receiver based on these results. Index Terms--Address-event, channel, communication, frame rate, interchip, scanning.

A VLSI architecture is proposed for the realization of real-time two-dimensional (2-D) image filtering in an address-event-representation (AER) vision system. The architecture is capable of implementing any convolutional kernel F(x, y) as long as it is decomposable into x-axis and y-axis components, i.e., F(x, y) = H(x) V(y), for some rotated coordinate system {x, y} and if this product can be approximated safely by a signed minimum operation. The proposed architecture is intended to be used in a complete vision system, known as the boundary contour system and feature contour system (BCS-FCS) vision model, proposed by Grossberg and collaborators. The present paper proposes the architecture, provides a circuit implementation using MOS transistors operated in weak inversion, and shows behavioral simulation results at the system level operation and some electrical simulations. Index Terms - Analog integrated circuits, communication systems, convolution circuits, Gabor filters, image analysis, image segmentation, neural networks, nonlinear circuits, subthreshold circuits.

We present an analog VLSI chip intended to serve as a front end of a speech recognition system. The chip architecture is inspired by biological auditory models common to humans and primate vertebrates. We include experimental results on a 1.2-[[micro]meter] CMOS custom analog VLSI implementation and speech recognition results obtained from software simulations of the hardware on the TI-DIGITS database. Index Terms - Analog VLSI, neural networks, speech recognition.