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On Test Generation for Microprocessors for Extended Class of Functional Faults
- Source :
- IFIP Advances in Information and Communication Technology, 27th IFIP/IEEE International Conference on Very Large Scale Integration-System on a Chip (VLSI-SoC), 27th IFIP/IEEE International Conference on Very Large Scale Integration-System on a Chip (VLSI-SoC), Oct 2019, Cusco, Peru. pp.21-44, ⟨10.1007/978-3-030-53273-4_2⟩, IFIP Advances in Information and Communication Technology ISBN: 9783030532727, VLSI-SoC (Selected Papers)
- Publication Year :
- 2019
- Publisher :
- HAL CCSD, 2019.
-
Abstract
- International audience; We propose a novel strategy of formalized synthesis of Software Based Self-Test (SBST) for testing microprocessors with RISC architecture to cover a large class of high-level functional faults. This is comparable to that used in memory testing which also covers a large class of structural faults such as stuck-at-faults (SAF), conditional SAF, multiple SAF and bridging faults. The approach is fully high-level, the model of the microprocessor is derived from the instruction set and architecture description, and no knowledge about gate-level implementation is needed. To keep the approach scalable, the microprocessor is partitioned into modules under test (MUT), and each MUT is in turn partitioned into data and control parts. For the data parts, pseudo-exhaustive tests are applied, while for the control parts, a novel generic functional control fault model was developed. A novel method for measuring high-level fault coverage for the control parts of MUTs is proposed. The measure can be interpreted as the quality of covering the high-level functional faults, which are difficult to enumerate. We apply High-Level Decision Diagrams for formalization and optimization of high-level test generation for control parts of modules and for trading off different test characteristics, such as test length, test generation time and fault coverage. The test is well-structured and can be easily unrolled online during test execution. Experimental results demonstrate high SAF coverage, achieved for a part of a RISC processor with known implementation, whereas the test was generated without knowledge of implementation details.
- Subjects :
- 010302 applied physics
Reduced instruction set computing
business.industry
Computer science
High-level functional fault model
Test generation
High-level fault coverage
02 engineering and technology
01 natural sciences
020202 computer hardware & architecture
law.invention
Instruction set
Microprocessor
Software
Computer engineering
law
0103 physical sciences
Scalability
Fault coverage
0202 electrical engineering, electronic engineering, information engineering
[INFO]Computer Science [cs]
Fault model
business
Software architecture description
Microprocessor testing
Subjects
Details
- Language :
- English
- ISBN :
- 978-3-030-53272-7
- ISBNs :
- 9783030532727
- Database :
- OpenAIRE
- Journal :
- IFIP Advances in Information and Communication Technology, 27th IFIP/IEEE International Conference on Very Large Scale Integration-System on a Chip (VLSI-SoC), 27th IFIP/IEEE International Conference on Very Large Scale Integration-System on a Chip (VLSI-SoC), Oct 2019, Cusco, Peru. pp.21-44, ⟨10.1007/978-3-030-53273-4_2⟩, IFIP Advances in Information and Communication Technology ISBN: 9783030532727, VLSI-SoC (Selected Papers)
- Accession number :
- edsair.doi.dedup.....64ec1b1638bf6b1dd16f71c6014f6da4
- Full Text :
- https://doi.org/10.1007/978-3-030-53273-4_2⟩