ALD metal-gate/high-κ gate stack for Si and Si/sub 0.7/Ge/sub 0.3/ surface-channel pMOSFETs

Authors :: A.-C. Lindgren
Eva Tois
Dongping Wu
Mikael Östling
Gustaf Sjöblom
S.-L. Zhang
Wei-Min Li
Jörgen Olsson
P.-E. Hellstrom
Marko Tuominen
E. Vainonen-Ahlgren
S. Persson
Source :: Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710).
Publication Year :: 2004
Publisher :: IEEE, 2004.
Abstract: ALD high-/spl kappa/ dielectrics and TiN metal-gate were successfully incorporated in both Si and Si/sub 0.7/Ge/sub 0.3/ surface-channel pMOSFETs. The high-/spl kappa/ gate dielectrics used included Al/sub 2/O/sub 3//HfAlO/sub x//Al/sub 2/O/sub 3/, Al/sub 2/O/sub 3//HfO/sub 2//Al/sub 2/O/sub 3/ and Al/sub 2/O/sub 3/. The Si transistors with Al/sub 2/O/sub 3//HfAlO/sub x//Al/sub 2/O/sub 3/ showed a sub-threshold slope of 75 mV/dec. and a density of interface states of 3/spl times/10/sup 11/ cm/sup -2/ eV/sup -1/. No obvious degradation of the Si channel hole mobility was observed. The Si/sub 0.7/Ge/sub 0.3/ pMOSFETs with the various high-/spl kappa/ gate dielectrics demonstrated enhanced transconductance, drive current and channel hole mobility compared with the Si reference.

Subjects :: Electron mobility
Atomic layer deposition
Materials science
chemistry
Silicon
Transconductance
MOSFET
Analytical chemistry
Electronic engineering
chemistry.chemical_element
Dielectric
Tin
Metal gate

Database :: OpenAIRE
Journal :: Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)
Accession number :: edsair.doi...........84b73b6af91dad6f1771fd5da61532f7
Full Text :: https://doi.org/10.1109/essderc.2003.1256864

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