Over Molding Process Development for a Stacked Wafer-level Chip Scale Package with Through Silicon Vias (TSVs)

Subjects

Subjects :

Materials science
Silicon
chemistry
Chip-scale package
Electronic engineering
Mechanical engineering
chemistry.chemical_element
Wafer
Compression (physics)

Details

ISSN :

18848028 and 18833365

Volume :

5

Database :

OpenAIRE

Journal :

Transactions of The Japan Institute of Electronics Packaging

Accession number :

edsair.doi...........6c35b1c8da46e59d231586edac967e44