Over Molding Process Development for a Stacked Wafer-level Chip Scale Package with Through Silicon Vias (TSVs)

MLA

Iriguchi Shoichi, et al. “Over Molding Process Development for a Stacked Wafer-Level Chip Scale Package with Through Silicon Vias (TSVs).” Transactions of The Japan Institute of Electronics Packaging, vol. 5, Jan. 2012, pp. 122–31. EBSCOhost, widgets.ebscohost.com/prod/customlink/proxify/proxify.php?count=1&encode=0&proxy=&find_1=&replace_1=&target=https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&scope=site&db=edsair&AN=edsair.doi...........6c35b1c8da46e59d231586edac967e44&authtype=sso&custid=ns315887.

APA

Iriguchi Shoichi, Yoshimi Takahashi, Philipp Steinmann, Yohei Koto, David C. Stepniak, Rajiv Dunne, Masazumi Amagai, & Tom Bonifield. (2012). Over Molding Process Development for a Stacked Wafer-level Chip Scale Package with Through Silicon Vias (TSVs). Transactions of The Japan Institute of Electronics Packaging, 5, 122–131.

Chicago

Iriguchi Shoichi, Yoshimi Takahashi, Philipp Steinmann, Yohei Koto, David C. Stepniak, Rajiv Dunne, Masazumi Amagai, and Tom Bonifield. 2012. “Over Molding Process Development for a Stacked Wafer-Level Chip Scale Package with Through Silicon Vias (TSVs).” Transactions of The Japan Institute of Electronics Packaging 5 (January): 122–31. http://widgets.ebscohost.com/prod/customlink/proxify/proxify.php?count=1&encode=0&proxy=&find_1=&replace_1=&target=https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&scope=site&db=edsair&AN=edsair.doi...........6c35b1c8da46e59d231586edac967e44&authtype=sso&custid=ns315887.