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A 50Gb/s CMOS Optical Receiver With Si-Photonics PD for High-Speed Low-Latency Chiplet I/O
- Source :
- Circuits and Systems I: Regular Papers, IEEE Transactions on; November 2023, Vol. 70 Issue: 11 p4271-4282, 12p
- Publication Year :
- 2023
-
Abstract
- This paper presents a 50-Gb/s optical receiver (ORX) chipset, consisting of a transimpedance amplifier (TIA) and a clock and data recovery (CDR) circuit in a 45-nm silicon-on-insulator CMOS. The proposed inverter-based TIA employs hybrid shunt-series peaking inductors to extend the bandwidth (BW). A baud-rate CDR is proposed to reduce the sampling phases and clocking power by half. To optimise the ORX for in- package integration, a compact-size digital loop is adopted in each channel, and the clock is recovered by phase interpolation from a shared reference. A complete optical-to-electrical (OE) link is built by integrating the proposed ORX with a high-speed Silicon Photonics (SiP) photodetector (PD). Measurements show that the proposed TIA has a transimpedance gain of 53 dB<inline-formula> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> and a BW of 27 GHz. By integrating it with the SiP PD, the OE front-end (PD+TIA) achieves an input sensitivity of −7.7 dBm at 50 Gb/s and BER<inline-formula> <tex-math notation="LaTeX">$ &lt; 10^{-12}$ </tex-math></inline-formula>. It features a power efficiency of 1.61 pJ/bit at a data rate of 64 Gb/s. The complete 50 Gb/s ORX achieves data recovery at a quarter rate of 12.5 Gb/s with an output jitter of 1.6 psrms, and has a 3.125 GHz clock with phase noise of −115.22 dBc/Hz at an offset frequency of 1 MHz.
Details
- Language :
- English
- ISSN :
- 15498328 and 15580806
- Volume :
- 70
- Issue :
- 11
- Database :
- Supplemental Index
- Journal :
- Circuits and Systems I: Regular Papers, IEEE Transactions on
- Publication Type :
- Periodical
- Accession number :
- ejs64349180
- Full Text :
- https://doi.org/10.1109/TCSI.2023.3314446