A 50Gb/s CMOS Optical Receiver With Si-Photonics PD for High-Speed Low-Latency Chiplet I/O

MLA

Chen, Sikai, et al. “A 50Gb/s CMOS Optical Receiver With Si-Photonics PD for High-Speed Low-Latency Chiplet I/O.” Circuits and Systems I: Regular Papers, IEEE Transactions On, vol. 70, no. 11, Nov. 2023, pp. 4271–82. EBSCOhost, https://doi.org/10.1109/TCSI.2023.3314446.

APA

Chen, S., You, M., Yang, Y., Jin, Y., Lin, Z., Li, Y., Li, L., Li, G., Xie, Y., Zhang, Z., Wang, B., Tang, N., Liu, F., Fang, Z., Liu, J., Wu, N., Chen, Y., Liu, L., Zhu, N., … Qi, N. (2023). A 50Gb/s CMOS Optical Receiver With Si-Photonics PD for High-Speed Low-Latency Chiplet I/O. Circuits and Systems I: Regular Papers, IEEE Transactions On, 70(11), 4271–4282. https://doi.org/10.1109/TCSI.2023.3314446

Chicago

Chen, Sikai, Mingyang You, Yunqi Yang, Ye Jin, Ziyi Lin, Yihong Li, Leliang Li, et al. 2023. “A 50Gb/s CMOS Optical Receiver With Si-Photonics PD for High-Speed Low-Latency Chiplet I/O.” Circuits and Systems I: Regular Papers, IEEE Transactions On 70 (11): 4271–82. doi:10.1109/TCSI.2023.3314446.