Back to Search
Start Over
Design and implementation of an algorithmic S/sup 2/I switched-current multiplier.
- Source :
- ISCAS '98 Proceedings of the 1998 IEEE International Symposium on Circuits & Systems (Cat No98CH36187); 1998, Issue 1, p37-37, 1p
- Publication Year :
- 1998
Details
- Language :
- English
- ISBNs :
- 9780780344556
- Issue :
- 1
- Database :
- Complementary Index
- Journal :
- ISCAS '98 Proceedings of the 1998 IEEE International Symposium on Circuits & Systems (Cat No98CH36187)
- Publication Type :
- Conference
- Accession number :
- 92192901
- Full Text :
- https://doi.org/10.1109/ISCAS.1998.704168