Design and implementation of an algorithmic S/sup 2/I switched-current multiplier.

MLA

Manganaro, G., and J. Pineda de Gyvez. “Design and Implementation of an Algorithmic S/Sup 2/I Switched-Current Multiplier.” ISCAS ’98 Proceedings of the 1998 IEEE International Symposium on Circuits & Systems (Cat No98CH36187), no. 1, Jan. 1998, p. 37. EBSCOhost, https://doi.org/10.1109/ISCAS.1998.704168.

APA

Manganaro, G., & Pineda de Gyvez, J. (1998). Design and implementation of an algorithmic S/sup 2/I switched-current multiplier. ISCAS ’98 Proceedings of the 1998 IEEE International Symposium on Circuits & Systems (Cat No98CH36187), 1, 37. https://doi.org/10.1109/ISCAS.1998.704168

Chicago

Manganaro, G., and J. Pineda de Gyvez. 1998. “Design and Implementation of an Algorithmic S/Sup 2/I Switched-Current Multiplier.” ISCAS ’98 Proceedings of the 1998 IEEE International Symposium on Circuits & Systems (Cat No98CH36187), no. 1 (January): 37. doi:10.1109/ISCAS.1998.704168.