A pseudo multi-bank DRAM with categorized access sequence.

Authors :: Shiratake, S.
Tsuchida, K.
Toda, H.
Kuyama, H.
Wada, M.
Kouno, F.
Inaba, T.
Akita, H.
Isobe, K.
Source :: 1999 Symposium on VLSI Circuits Digest of Papers (IEEE Cat No99CH36326); 1999, p127-130, 4p
Publication Year :: 1999

Language :: English
ISBNs :: 9784930813954
Database :: Complementary Index
Journal :: 1999 Symposium on VLSI Circuits Digest of Papers (IEEE Cat No99CH36326)
Publication Type :: Conference
Accession number :: 92140554
Full Text :: https://doi.org/10.1109/VLSIC.1999.797260