A pseudo multi-bank DRAM with categorized access sequence.

MLA

Shiratake, S., et al. “A Pseudo Multi-Bank DRAM with Categorized Access Sequence.” 1999 Symposium on VLSI Circuits Digest of Papers (IEEE Cat No99CH36326), Jan. 1999, pp. 127–30. EBSCOhost, https://doi.org/10.1109/VLSIC.1999.797260.

APA

Shiratake, S., Tsuchida, K., Toda, H., Kuyama, H., Wada, M., Kouno, F., Inaba, T., Akita, H., & Isobe, K. (1999). A pseudo multi-bank DRAM with categorized access sequence. 1999 Symposium on VLSI Circuits Digest of Papers (IEEE Cat No99CH36326), 127–130. https://doi.org/10.1109/VLSIC.1999.797260

Chicago

Shiratake, S., K. Tsuchida, H. Toda, H. Kuyama, M. Wada, F. Kouno, T. Inaba, H. Akita, and K. Isobe. 1999. “A Pseudo Multi-Bank DRAM with Categorized Access Sequence.” 1999 Symposium on VLSI Circuits Digest of Papers (IEEE Cat No99CH36326), January, 127–30. doi:10.1109/VLSIC.1999.797260.