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Dynamic Reconfigurable Architecture Exploration based on Parameterized Reconfigurable Processor Model.

Authors :
De Micheli, Giovanni
Mir, Salvador
Reis, Ricardo
Taniguchi, Ittetsu
Sakanushi, Keishi
Ueda, Kyoko
Takeuchi, Yoshinori
Imai, Masaharu
Source :
VLSI-SoC: Research Trends in VLSI & Systems on Chip; 2008, p357-376, 20p
Publication Year :
2008

Abstract

In recent years, dynamic reconfigurable processor which can achieve reconfiguration with a few cycles is proposed. The fast recon- figuration makes run-time reconfiguration possible, and the run-time reconfiguration gives a new possibility to the dynamic reconfigurable processor, i.e. the dynamic reconfigurable processor can also execute partitioned independent subtasks with repeated reconfigurations and executions. However, to achieve an execution with the run-time reconfiguration, performance should be evaluated with various overheads: reconfiguration, memory accesses, etc. The overheads depend on reconfigurable architectures, and it is generally difficult to evaluate the overhead. As the overhead may critically affect the performance, designers should carefully explore design space for suitable architectures. In this paper, we propose a dynamic reconfigurable architecture exploration method based on Parameterized Reconfigurable Processor model (PRP-model) and task partitioning optimization algorithm for architecture exploration corresponding to proposed PRP-model. Experimental results showed that the proposed PRP-model and the task partitioning algorithm for PRP-model can fast evaluate various reconfigurable architectures, and designers can easily find suitable reconfigurable architectures by changing the PRPmodel parameters. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISBNs :
9780387749082
Database :
Complementary Index
Journal :
VLSI-SoC: Research Trends in VLSI & Systems on Chip
Publication Type :
Book
Accession number :
33878865
Full Text :
https://doi.org/10.1007/978-0-387-74909-9_20