A Novel Programming Technique to Boost Low-Resistance State Performance in Ge-Rich GST Phase Change Memory.

In this paper, we examine the problem of the drift of the low-resistance state (LRS) in phase change memories based on C or N doped and undoped Ge-rich Ge2Sb2Te5 . A novel procedure, named R–SET technique, is proposed to boost the SET speed of these innovative phase change materials by overcoming the decrease of crystallization speed caused by Ge enrichment. The R–SET technique allows, at the same time, an optimized SET programming of the memory cell and the reduction of the LRS drift with respect to standard SET procedures. A circuit that generates the desired R–SET pulse based on a time reference scheme is proposed and discussed. [ABSTRACT FROM PUBLISHER]