Back to Search
Start Over
Design of Test Structures for the Characterization of Thermal–Mechanical Stress in 3D-Stacked IC.
- Source :
-
IEEE Transactions on Semiconductor Manufacturing . Aug2012, Vol. 25 Issue 3, p365-371. 7p. - Publication Year :
- 2012
-
Abstract
- In this paper, we present test structures and measurement techniques that enable the extraction of the significance of the thermal–mechanical stress in 3D-stacked integrated circuit technology. Heaters and integrated diodes have been used to determine the impact of hotspots in 3-D systems. The results obtained showed that in 3-D case, the peak temperature of a hotspot is three times higher compared to a traditional 2-D system. For the characterization of through silicon vias (TSVs)-induced stress and its impact on analog metal-oxide semiconductor (MOS) devices, a 10-bit current steering digital-to-analog converter (DAC) test structure is utilized. The DAC has been optimized to detect ion changes down to 0.5% due to TSV proximity, TSV orientation, thermal hotspots, and wafer thinning or stacking process. The results obtained from stand-alone short-channel MOS devices and the DAC structure clearly indicate the impact of TSV proximity and TSV orientation on the carrier mobility of nearby transistors. [ABSTRACT FROM PUBLISHER]
Details
- Language :
- English
- ISSN :
- 08946507
- Volume :
- 25
- Issue :
- 3
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Semiconductor Manufacturing
- Publication Type :
- Academic Journal
- Accession number :
- 79466626
- Full Text :
- https://doi.org/10.1109/TSM.2012.2202809