Cite
Design of Test Structures for the Characterization of Thermal–Mechanical Stress in 3D-Stacked IC.
MLA
Minas, Nikolaos, et al. “Design of Test Structures for the Characterization of Thermal–Mechanical Stress in 3D-Stacked IC.” IEEE Transactions on Semiconductor Manufacturing, vol. 25, no. 3, Aug. 2012, pp. 365–71. EBSCOhost, https://doi.org/10.1109/TSM.2012.2202809.
APA
Minas, N., Van der Plas, G., Oprins, H., Yang, Y., Okoro, C., Mercha, A., Cherman, V., Torregiani, C., Perry, D., Cupak, M., Rakowski, M., & Marchal, P. (2012). Design of Test Structures for the Characterization of Thermal–Mechanical Stress in 3D-Stacked IC. IEEE Transactions on Semiconductor Manufacturing, 25(3), 365–371. https://doi.org/10.1109/TSM.2012.2202809
Chicago
Minas, Nikolaos, Geert Van der Plas, Herman Oprins, Yu Yang, Chukwudi Okoro, Abdelkarim Mercha, Vladimir Cherman, et al. 2012. “Design of Test Structures for the Characterization of Thermal–Mechanical Stress in 3D-Stacked IC.” IEEE Transactions on Semiconductor Manufacturing 25 (3): 365–71. doi:10.1109/TSM.2012.2202809.