Hope seen for taming IC process variability at next design node.

Information about several papers discussed at the International Symposium on Physical Design held in April 2006 in San Jose, California is presented. New chip design at 65 nanometers where temperature, voltage and process variations have dramatic impact on chip timing, manufacturability and yield were offered during the symposium. It also featured several authors from the University of California in Los Angeles and International Business Machine Research who received ISPD 2006 Best Paper Award.