Implementation of optimized ternary AND gate using 18nm FinFET.

Fast-growing computer technology and digital system integration complicate nano-scale binary logic circuit design. Ternary logic circuits offer an alternative to binary circuits in digital electronics, adding '2' to '0' and '1'. The added state reduces computational complexity, boosting system power and efficiency. This article discusses developing ternary logic circuits utilizing various nodes and semiconductor components. In addition, this paper explores the implementation of a ternary logic AND gate using the Cadence Virtuoso platform's VerilogA hardware description language. The implementation of a device model for a FinFET with a changeable threshold voltage of 18nm has been completed. The circuit has been adjusted to provide the desired logical output by manipulating the number of fins in the FinFET Model. The high threshold voltage (HVT) model exhibits superior performance parameters in terms of power and delay. The power delay product of HVT model is 56.7% and 31.8% lower than the LVT and SVT models respectively. [ABSTRACT FROM AUTHOR]