Implementation of optimized ternary AND gate using 18nm FinFET.

MLA

Gupta, Lipika, et al. “Implementation of Optimized Ternary AND Gate Using 18nm FinFET.” AIP Conference Proceedings, vol. 3209, no. 1, Aug. 2024, pp. 1–7. EBSCOhost, https://doi.org/10.1063/5.0228052.

APA

Gupta, L., Dassi, M., Goyal, M., & Sharma, K. (2024). Implementation of optimized ternary AND gate using 18nm FinFET. AIP Conference Proceedings, 3209(1), 1–7. https://doi.org/10.1063/5.0228052

Chicago

Gupta, Lipika, Minaxi Dassi, Mohit Goyal, and Kulbhushan Sharma. 2024. “Implementation of Optimized Ternary AND Gate Using 18nm FinFET.” AIP Conference Proceedings 3209 (1): 1–7. doi:10.1063/5.0228052.