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In this paper, we present a framework of modeling memristor noise for circuit simulators using physics-informed neural networks (PINNs). The variability of the memristor that is directly related to the neuromorphic system can be handled with this approach. The memristor noise model is transformed into a Fokker–Planck equation (FPE) from a probabilistic perspective. The translated equations are physically interpreted through the PINN. The weights and biases extracted from the PINN are implemented in Verilog-A through simple operations. The characteristics of the stochastic system under the noise are obtained by integrating the probability density function. This approach allows for the unification of different memristor models and the analysis of the effects of noise. [ABSTRACT FROM AUTHOR]

The thermometer digital-to-analog converter (DAC) is a distinctive architecture that plays a vital role in converting digital data into corresponding analog signals, the thermometer DAC employs a resistor network where each bit of the digital input corresponds to a unique resistor. It has notable drawbacks that need careful consideration. As the resolution of the DAC increases, the number of required current sources grows exponentially, leading to complex and demanding circuitry. This can escalate power consumption and occupy significant chip area, which is a critical concern in integrated circuit design. Furthermore, the current mismatch between the multiple current sources. Therefore, integrating memristors into DACs paves the way for more compact and efficient designs, reducing system complexity and enhancing reliability. The Voltage ThrEshold Adaptive Memristor (VTEAM) model of memristor is validated by using Virtuoso. In addition, a digital-to-analog converter based on memristor technology is implemented, taking advantage of the memristor's compact size, minimal power usage, and a voltage threshold that is relatively low. The DAC design being proposed is based on a core DAC cell that consists of two memristors connected in opposing orientations. [ABSTRACT FROM AUTHOR]

In this paper, we present a framework of modeling memristor noise for circuit simulators using physics-informed neural networks (PINNs). The variability of the memristor that is directly related to the neuromorphic system can be handled with this approach. The memristor noise model is transformed into a Fokker–Planck equation (FPE) from a probabilistic perspective. The translated equations are physically interpreted through the PINN. The weights and biases extracted from the PINN are implemented in Verilog-A through simple operations. The characteristics of the stochastic system under the noise are obtained by integrating the probability density function. This approach allows for the unification of different memristor models and the analysis of the effects of noise.

Memristor devices have diverse physical models depending on their structure. In addition, the physical properties of memristors are described using complex differential equations. Therefore, it is necessary to integrate the various models of memristor into an unified physics-based model. In this paper, we propose a physics-informed neural network (PINN)-based compact memristor model. PINNs can solve complex differential equations intuitively and with ease. This methodology is used to conduct memristor physical analysis. The weight and bias extracted from the PINN are implemented in a Verilog-A circuit simulator to predict memristor device characteristics. The accuracy of the proposed model is verified using two memristor devices. The results show that PINNs can be used to extensively integrate memristor device models. [ABSTRACT FROM AUTHOR]

The most notable accumulation of trap charges occurs on the oxide/semiconductor interface of MOS devices and it degrades the device's performance and reliability. In this literature, we proposed a gate-engineered Schottky tunneling MOSFET(GE-ST-MOSFET) for ON state performance improvement, and a detailed analysis of the effects of interface trap charges (ITCs) on the DC characteristics and analog/RF performance metrics have been analyzed. In this device, the electrostatically doping-based dopant segregation layer (DSL) is introduced at the source side in the channel end by the Tunneling Gate(TG). A comparative study between the proposed GE-ST-MOSFET and conventional Schottky tunneling MOSFET(ST-MOSFET) has been carried out in presence of interface trap charges at the HfO 2 /Si interface. A significant improvement in I ON and I ON / I OFF ratio has been achieved 563 × and 1472 × respectively in the GE-ST-MOSFET as compared to the ST-MOSFET. To analyze the linearity behavior, higher-order transconductance parameters are also studied considering the effect of ITCs. Furthermore, the circuit-level performances of both devices are analyzed using the Verilog-A based models. The effect of OFF current variation on switching performance has been investigated. It has been found that the average switching delay and Power Delay Product (PDP) have improved by 97% and 81% respectively in comparison to the conventional device-based inverter. The GE-ST-MOSFET-based circuit also shows better immunity to interface trap charges. In addition, the implementation of the electrostatically doping concept for the proposed device could make fabrication very simple. [ABSTRACT FROM AUTHOR]

This paper presents a new time domain Zener diode compact model for transient noise simulation. SPICE2 and SPIC3 use piece‐wise linear time dependent sources for generating complex waveforms. This approach is not practical when applied to randomly generated noise. Today, through on‐going improvements to freely available circuit simulation tools, SPICE noise generation has moved to a new level. Ngspice, for example, computes white Gaussian noise 'on‐the‐fly' as transient simulation progresses. The proposed model has a simple behavioural structure that supports time domain shot, flicker, and thermal noise. The physical properties of the proposed model are introduced in the second section. This is followed by an evaluation of model performance in the third and fourth sections, including static d.c, dynamic charge, and transient noise characterisation. Finally, the fifth section summarises the conclusions of the research. [ABSTRACT FROM AUTHOR]

The article investigates the performance of germanium source doping-less tunnel FET (Ge DLTFET)-based digital integrated circuits. For this, the compact models have been developed for DLTFETs using Verilog-A approach. Furthermore, at circuit level, the performance of Ge DLTFET is compared with its conventional counterpart silicon source DLTFET (Si DLTEFT). Two digital benchmark circuits are considered for circuit simulation such as ring oscillator (RO) and conventional six-transistor static random-access memory (6 T SRAM). The simulation results depict that the operating frequency of Ge DLTFET RO is ~ 4.48 decade higher than Si DLTFET. Similarly, the performance of Ge DLTFET SRAM cell in terms of read and write delay is much better than its conventional counterpart Si DLTFET. Hence, Ge DLTFET can be considered as a promising device structure for high-speed digital circuit design and for its applications. [ABSTRACT FROM AUTHOR]

A thermally agitated device model of spin-transfer torque magnetic tunnel junction (STT-MTJ) based on the Fokker-Planck equation is proposed which is implemented into HSPICE by using Verilog-A. We compared different techniques of finite difference method (FDM) and analyzed the impact of the solvers on computational efficiency and accuracy. A framework is proposed which traces dynamics of a particular STT-MTJ's angle between the magnetic moments of the free and the pinned layers and makes the model applicable to a wide range of circuits. The model was applied to the 4T2MTJ memory cell array and a leaky integrate-and-fire (LIF) neuron circuit to validate the stochastic switching characteristic and the angle prediction function. In the memory array simulations, the CPU time consumption for this model is 1/30 of the model which is based on the stochastic Landau-Lifshitz-Gilbert-Slonczewski equation. [ABSTRACT FROM AUTHOR]

In this article, the performance of 3-D nanosheet FET (NS-FET) in inversion (INV) and junctionless (JL) modes is demonstrated and compared at both device and circuit levels. In JL mode, the ON current ( $I_{\mathrm {ON}}$ ) rises with an increase in temperature compared to the downfall trend in INV mode. In addition, compared to JL mode, the INV mode exhibits a better negative temperature coefficient of threshold voltage ( $\text{d}V_{\mathrm {th}}$ /dT). Further, the mixed mode circuit simulations are carried out using the Cadence Virtuoso platform through the Verilog-A model. From the analysis, it is observed that an increase of 20% gain in INV mode compared to JL mode for a common source (CS) amplifier. The JL mode NS-FETs achieve higher CMOS inverter switching current ( $I_{SC}$ ) and lower energy-delay products (EDP) as temperature rises. A three-stage ring oscillator (RO) is designed, and the oscillation frequencies ( $f_{\mathrm {OSC}}$ ) of 43.39 GHz and 38.8 GHz are obtained with INV and JL modes. Although JL NS-FET offers less intrinsic capacitances, the $f_{\mathrm {OSC}}$ is high for INV mode due to higher $I_{\mathrm {ON}}$ . Furthermore, reducing supply voltage ( $V_{\mathrm {DD}}$ ), the $f_{\mathrm {OSC}}$ falls by 67% with INV and 62.6% with JL modes. These results will give a better understanding of this emerging NS-FET at both device and circuit levels at advanced technology nodes.

In this paper the design of regulated active rectifiers (RARs) is addressed, with emphasis on energy harvesting applications. After an insightful overview of the main topologies of RARs, the analytical models are discussed and extended. Then, a data-driven comparison is carried out which, however, does not allows an absolute ranking between the different topologies. Then, a general Verilog-A model of the active rectifier is introduced and extended to simulate and compare the different regulation schemes. Unlike the data-driven comparison, the simulations based on the proposed Verilog-A models allows concluding that the PWM regulation scheme is more suitable for applications requiring an input power lower than about 1mW, whereas the Reconfigurable (1X/0X) is more effective for input power levels in the range 1mW-10mW. The adoption of the developed models allows a huge reduction of the simulation time, equal to 7X for the open loop active rectifier and about 100X for the regulated mode. The accuracy of the proposed model has been extensively verified against transistor-level simulations, showing an error lower than 5% in all conditions. The proposed model is useful during the design phase to select the rectifier topology and control scheme during the design phase and also to reduce the simulation time during pre-silicon verification on complex mixed-signal systems.

This paper presents the behavioral modeling of three circuit architectures, which are suitable for heartbeat detection in wireless healthcare applications. The developed front-end models implement an analog system that detects the heartbeats for lower power consumption and higher detection accuracy without digital signal processing. Therefore, the circuit blocks and their critical specifications specifically regarding the noise and bandwidth are evaluated. The architectures are implemented in Verilog-A and their behavior simulations use real electrocardiogram (ECG) signals with different characteristics and conditions. All architectures have amplification, band-pass and notch response blocks as their first three stages. Then, the first circuit architecture detects the heartbeat using an adaptive threshold based on a pulse width approach. The second heartbeat detection scheme finds the maximum and minimum values of each beat using a sample-and-hold-based peak detector. The third model uses a similar peak detection scheme, but delays the analog signal for better precision. The simulation results show that all models can detect heartbeats when the input noise is less than $20 \mu V$ , the third having the highest noise tolerance of around $50 \mu V$ . For the ECG signal to maintain its characteristics with respect to its positive and negative peak, the bandpass response should present a low cutoff frequency below 10 Hz.

The 1S1R storage unit of 3D phase-change memory is composed of ovonic threshold switch selector (OTS) in series with the phase change memory (PCM) device. In order to solve the problems of the current OTS and PCM circuit simulation models, such as not able to accurately simulate the electrical and physical characteristics of devices, and not suitable for confined PCM, a 1S1R spice model based on Verilog-A is proposed. The model simulates the electrical characteristics of OTS and the changes of current, temperature, melting proportion, crystallization proportion and amorphous proportion in the crystallization, melting and quenching of the PCM. The model has a good convergence and fast simulation speed. The simulation results are consistent with the actual test results of the device. Compared with the traditional model, the simulation and integration of confined PCM melting process, crystal nonlinearity, melting resistivity stability and subthreshold nonlinearity, and bidirectional switching characteristics of OTS are realized. The relationship between OTS subthreshold nonlinear parameter and read voltage window is analyzed. It is found that the read window reaches its maximum when OTS threshold current is approximately equal to PCM threshold current. The results of DC simulation of 1S1R cell and transient simulation of array are displayed, providing the basis for circuit design and simulation of 3D phase-change memory.

Memristor devices have diverse physical models depending on their structure. In addition, the physical properties of memristors are described using complex differential equations. Therefore, it is necessary to integrate the various models of memristor into an unified physics-based model. In this paper, we propose a physics-informed neural network (PINN)-based compact memristor model. PINNs can solve complex differential equations intuitively and with ease. This methodology is used to conduct memristor physical analysis. The weight and bias extracted from the PINN are implemented in a Verilog-A circuit simulator to predict memristor device characteristics. The accuracy of the proposed model is verified using two memristor devices. The results show that PINNs can be used to extensively integrate memristor device models.

A compact model able to predict the electrical read-out of field-effect biosensors based on two-dimensional (2D) semiconductors is introduced. It comprises the analytical description of the electrostatics including the charge density in the 2D semiconductor, the site-binding modeling of the barrier oxide surface charge, and the Stern layer plus an ion-permeable membrane, all coupled with the carrier transport inside the biosensor and solved by making use of the Donnan potential inside the ion-permeable membrane formed by charged macromolecules. This electrostatics and transport description account for the main surface-related physical and chemical processes that impact the biosensor electrical performance, including the transport along the low-dimensional channel in the diffusive regime, electrolyte screening, and the impact of biological charges. The model is implemented in Verilog-A and can be employed on standard circuit design tools. The theoretical predictions obtained with the model are validated against measurements of a MoS2 field-effect biosensor for streptavidin detection showing excellent agreement in all operation regimes and leading the way for the circuit-level simulation of biosensors based on 2D semiconductors. [ABSTRACT FROM AUTHOR]

In the present research article, we have proposed an analytical compact model for nanowire Junctionless Gate-All-Around (JLNGAA) MOSFET validated in all transistor's operation regimes. The developed model having an analytical compact form of the current expressions, based on surface potential (ΦS), obtained from approximated solutions of Poisson's equation. The proposed model has implemented in standard Verilog-A language using SMASH circuit simulator in order to be used in various commercial circuit simulators. The proposed model has also validated using ATLAS-TCAD simulation for various physical parameters such as the channel doping concentration (Nd) and the channel radius (R) of JLNGAA MOSFET. Finally, based on the developed Verilog-A JLNGAA MOSFET model, we have tested it in four types of low voltage circuits, CMOS inverter, CMOS NOR-Gate, an amplifier and a Colpitts oscillator. [ABSTRACT FROM AUTHOR]

This work presents a behavioral model for a microelectromechanical (MEM) relay for use in circuit simulation. Models require calibration, and other published relay models require over a dozen parameters for calibration, many of which are difficult to extract or are only available after finite element analysis. This model improves on prior work by taking advantage of model normalization, which often results in models that require fewer parameters than un-normalized models. This model only needs three parameters extracted from experiment and one dimension known from device fabrication to represent its non-contact behavior, and two additional extracted parameters to represent its behavior when in contact. The extracted parameters–quality factor, resonant frequency, and the pull-in voltage–can be found using laser Doppler vibrometry. The device dimension is the actuation gap size, which comes from process data. To demonstrate this extraction process, a series of velocity step responses were excited in MEM relays, the measured velocity responses were used to calibrate the model, and then then simulations of the model (implemented in Verilog-A) were compared against the measured data. The error in the simulated oscillation frequency and peak velocity, two values selected as figures of merit, is less than 10% across many operating voltages. [ABSTRACT FROM AUTHOR]

In this article, FinFET, vertically stacked gate-all-around (GAA) nanowire (NW), and nanosheet (NS) FETs performance are estimated with equal effective channel widths (${W}_{eff}$) at the 5-nm technology node (N5). The comparison reveals that NS FET exhibits the highest ON current (${I}_{ \mathrm{\scriptscriptstyle ON}}$), the lowest OFF current (${I}_{ \mathrm{\scriptscriptstyle OFF}}$), and the largest ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio with better subthreshold performance. We also explore the geometrical variation of the NS FET toward better dc and analog/RF applications and outlined the necessary design guidelines. Moreover, the robustness of NS FET for temperature variations is also performed and analyzed. Finally, the effect of NS width ($\text{NS}_{W}$) on common source (CS) amplifier, CMOS inverter, and ring oscillator circuits is performed by the Verilog-A model in the CADENCE simulator. An increment of 45.11% in oscillation frequency ($f_{osc}$), 155.5% rise in CS amplifier gain, $2.5\times $ increment in energy-delay product (EDP), and marginal reduction in inverter noise margin (NM) is noticed with larger $\text{NS}_{W}$. From the result analysis, it is noticed that for sub-5-nm technological nodes, NS FETs exhibit superior performance and ensure fundamental scaling. [ABSTRACT FROM AUTHOR]

Almost 50% of random logic power is consumed in System-on-chip (SOC) by the memory latch circuits. VLSI designers of high performance SOC are struggling to realise a performance rich and energy efficient design method. A number of power optimisation techniques and methods have been suggested which ultimately increase hardware complexity. Consequently, due to more number of components the cost as well as the area used on chip increases. In this study the design and demonstration of D latch and S-R latch based on the Silicene based multiplexer device (SMLD) using Verilog-A is done. The working of SMLD based latches is validated through circuits simulations in SPICE. The SMLD based D latch and S-R latch show an improvement in hardware reduction by 93.75% and 50% respectively as compared to CMOS based D latch and S-R latch. Also the improvement in area utilization on chip by 94.10% and 52.83% is achieved by SMLD based D latch and S-R latch respectively. [ABSTRACT FROM AUTHOR]

In this article, analog/radio frequency (RF) performance metrics along with linearity analysis of a silicon-on-insulator lightly doped drain (LDD)-finFET are investigated through 3D TCAD simulations. The inclusion of LDD regions in the finFET architecture reduces the electric field by 15.3% in the locality of the drain junction. RF efficiency metrics including intrinsic gate delay, transconductance generation factor , unity–gain bandwidth, and energy and power dissipation, along with the subthreshold performance of the proposed device, are compared with the traditional finFET. Device linearity parameters including second- and third-order voltage intercept point, third-order intercept point, and third-order intermodulation point are analyzed to test their accuracy and reliability. Look-up table-based Verilog-A simulations are performed to obtain the circuit-level performance of the finFET structure. Mixed-signal circuits including ring oscillator and operational transconductance amplifier are designed and investigated for 22-nm LDD-finFET technology and compared with the existing works available in the literature. We achieved an improvement of 27.59% in oscillation frequency and a maximum common-mode rejection ratio (CMRR) of 83.45 dB as compared to Si-MOSFET-based circuits. [ABSTRACT FROM AUTHOR]

In this paper, a compact model for the double-gate Reconfigurable Field-Effect Transistor (RFET) is presented. Firstly, the physics-based surface potential model is derived by solving Poisson’s equation at different channel regions. Then an explicit expression of drain current is analytically obtained based on the theory of band-to-band tunneling at the Schottky junction. The proposed model shows excellent agreement with TCAD simulations which have been calibrated with experimental data. Finally, the compactible model is implemented in Verilog-A language without convergence problem, and proven by the RFET-based logic circuit.

The Analytical Full Capacitance Model (AFCM) for amorphous oxide semiconductors thin film transistors (AOSTFTs) is first validated, using a 19-stages Ring Oscillator (RO) fabricated and measured. The model was described in Verilog-A language to use it in a circuit simulator in this case SmartSpice from Silvaco. The model includes the extrinsic effects related to specific overlap capacitances present in bottom-gate AOSTFT structures. The dynamic behavior of the simulated circuit, when the TFT internal capacitances are increased or decreased and for different supply voltages of 10, 15 and 20 V, is compared with measured characteristics, obtaining a very good agreement. Afterwards, the AFCM is used to simulate the dynamic behavior of a pixel control circuit for a light emitting diode active matrix display (AMOLED), using an AOSTFT.

An accurate and efficient noise-based simulation technique for predicting the impact of device-parameter variability on the DC statistical behavior of integrated circuits is presented. The proposed method is validated on a source follower, a diode-load inverter and a current mirror based on organic thin-film transistors. Taking advantage of the standard noise analysis of a circuit, after translating the statistical variation of the electrical parameters of the transistors into equivalent-noise circuit components, the proposed technique yields results identical to those obtained from a Monte Carlo simulation, but in a significantly shorter amount of time.

Process validation test (PVT) helps to predict the response of a device to various figure of merit (FOM) parameters, such as diameter (process), supply voltage, and temperature. In this paper, the Stanford model is modified to investigate the effect of temperature, nanotube diameter, etc. on the current-voltage characteristics, drain current, transconductance, threshold voltage, subthreshold swing, and conductance of Carbon Nanotube Field Effect Transistors (CNTFETs). To study different parameters in terms of temperature in CNTFETs, we simulate different circuits by adding temperature-dependent voltage/current equations and defining temperature as a parameter in the Stanford model. The results show that an increase in temperature results in higher subthreshold swing, lower on/off current ratio, and lower threshold voltage. Moreover, by adding the variable diameter to the model, we examine its effect on different CNTFET parameters. As diameter increases, both the on/off current ratio and subthreshold swing increase, so the net effect is almost the same. CNTFET noise model is translated in Verilog-A, and then implemented in the ADS simulator. The results show that the shot noise is more noticeable at high frequencies and the flicker noise at low frequencies. Moreover, the noise figure of CNTFET is higher at lower frequencies. [ABSTRACT FROM AUTHOR]

In this paper, an empirical model of dual gate graphene field-effect transistor (GFET) has been developed. The explicit form of drain current expression has been established analytically based on a drift-diffusion approach. The channel sheet charge density helps us to determine the quantum capacitance more accurately. The channel potential has been derived from the equivalent circuit. The improvement of carrier mobility has been included. The closed form expression is obtained with a few fitting parameters to explore the model characteristics. The model is also valid for single gate technology. The model has been verified against some pioneering experimental results reported in literatures. Model simulation agrees well with existing experimental data. We have also compared the results of the model obtained from NANOHUB online simulator for further verification. The characteristics of small signal parameters of this GFET model have been observed and cut-off frequency has been determined. The developed analytical GFET model is also found to be computationally efficient. It is observed that with ± 10% variation in top gate oxide thickness, maximum drain current and peak transconductance vary by (−11.53%/ + 14%) and (−25%/+31.25%), respectively. The double gate bilayer GFET model is implemented in Verilog-A and verified for a voltage amplifier in SPICE environment. [ABSTRACT FROM AUTHOR]

Although the compact capacitance model of point tunneling types of tunneling field-effect transistors (TFET) has been proposed, those of line tunneling types of TFETs have not been reported. In this study, a compact capacitance model of an L-shaped TFET (LTFET), a line tunneling type of TFET, is proposed using the previously developed surface potentials and current models of Pand L-type LTFETs. The Verilog-A LTFET model for simulation program with integrated circuit emphasis (SPICE) was also developed to verify the validation of the compact LTFET model including the capacitance model. The SPICE simulation results using the Verilog-A LTFET were compared to those obtained using a technology computer-aided-design (TCAD) device simulator. The current–voltage characteristics and capacitance–voltage characteristics of N and P-LTFETs were consistent for all operational bias. The voltage transfer characteristics and transient response of the inverter circuit comprising N and PLTFETs in series were verified with the TCAD mixed-mode simulation results. [ABSTRACT FROM AUTHOR]

We present a physics-based circuit-compatible model for pH-sensitive field-effect transistors based on 2-D materials. The electrostatics along the electrolyte-gated 2-D-semiconductor stack is treated by solving the Poisson equation, including the site-binding model and the Gouy–Chapman–Stern approach, while the carrier transport is described by the drift-diffusion theory. The proposed model is provided in an analytical form and then implemented in Verilog-A, making it compatible with standard technology computer-aided design tools employed for circuit simulation. The model is benchmarked against two experimental transition-metal-dichalcogenide (MoS2 and ReS2)-based ion sensors, showing excellent agreement when predicting the drain current, threshold voltage shift, and current/voltage sensitivity measurements for different pH concentrations. [ABSTRACT FROM AUTHOR]

This work reports a compact behavioral model for gated-synaptic memory. The model is developed in Verilog-A for easy integration into computer-aided design of neuromorphic circuits using emerging memory. The model encompasses various forms of gated synapses within a single framework and is not restricted to only a single type. The behavioral theory of the model is described in detail along with a full list of the default parameter settings. The model includes parameters, such as a device’s ideal set time, threshold voltage, general evolution of the conductance with respect to time, decay of the device’s state, etc. Finally, the model’s validity is shown via extensive simulation and fitting to experimentally reported data on published gated-synapses. [ABSTRACT FROM AUTHOR]

In the asynchronous time-based image sensor (ATIS) pixel, capture is performed only when a significant luminance change is detected, thus avoiding redundant transmission of data. Furthermore, luminance capture is performed by generating events when the photodiode voltage crosses two thresholds, at the pixel level, which contributes to a high dynamic range in image capture. The ATIS disadvantages are large pixel area and low fill factor. In order to reduce the pixel area, we propose the design of an ATIS in which the dynamic vision sensor (DVS) module is shared by a block of capture modules. A pixel with a 2 × 2 sharing block has roughly 29% fewer components than a pixel with one DVS module per capture module. A Verilog-A model of the proposed circuit is presented and compared to the electrical (device-level) model. Due to the mixed-signal nature of the circuit, the Verilog-A is an important tool for increasing simulation speed. We show that the Verilog-A model simulation of a 4 × 4 matrix is 70% faster than the electrical device-level simulation, while yielding similar reconstruction results. [ABSTRACT FROM AUTHOR]

Resistive random-access memory (RRAM) devices have drawn increasing interest for the simplicity of its structure, low power consumption and applicability to neuromorphic computing. By combining analog computing and data storage at the device level, neuromorphic computing system has the potential to meet the demand of computing power in applications such as artificial intelligence (AI), machine learning (ML) and Internet of Things (IoT). Monolayer rhenium diselenide (ReSe2), as a two-dimensional (2D) material, has been reported to exhibit non-volatile resistive switching (NVRS) behavior in RRAM devices with sub-nanometer active layer thickness. In this paper, we demonstrate stable multiple-step RESET in ReSe2 RRAM devices by applying different levels of DC electrical bias. Pulse measurement has been conducted to study the neuromorphic characteristics. Under different height of stimuli, the ReSe2 RRAM devices have been found to switch to different resistance states, which shows the potentiation of synaptic applications. Long-term potentiation (LTP) and depression (LTD) have been demonstrated with the gradual resistance switching behaviors observed in long-term plasticity programming. A Verilog-A model is proposed based on the multiple-step resistive switching behavior. By implementing the LTP/LTD parameters, an artificial neural network (ANN) is constructed for the demonstration of handwriting classification using Modified National Institute of Standards and Technology (MNIST) dataset.

This work presents a behavioral model for a microelectromechanical (MEM) relay for use in circuit simulation. Models require calibration, and other published relay models require over a dozen parameters for calibration, many of which are difficult to extract or are only available after finite element analysis. This model improves on prior work by taking advantage of model normalization, which often results in models that require fewer parameters than un-normalized models. This model only needs three parameters extracted from experiment and one dimension known from device fabrication to represent its non-contact behavior, and two additional extracted parameters to represent its behavior when in contact. The extracted parameters–quality factor, resonant frequency, and the pull-in voltage–can be found using laser Doppler vibrometry. The device dimension is the actuation gap size, which comes from process data. To demonstrate this extraction process, a series of velocity step responses were excited in MEM relays, the measured velocity responses were used to calibrate the model, and then then simulations of the model (implemented in Verilog-A) were compared against the measured data. The error in the simulated oscillation frequency and peak velocity, two values selected as figures of merit, is less than 10% across many operating voltages.

Voltage controlled oscillators (VCOs) are used as key components in phase‐locked loop systems for generating stable oscillation signals. Since the digital electronics industry increasingly needs a faster operation, VCOs need to generate signals at higher frequencies. This paper presents a voltage controlled oscillator with a wide frequency range and very low phase noise by using carbon nanotube technology. The Stanford CNTFET model is implemented in Verilog‐A, and the proposed CNTFET VCO is simulated using ADS software. Simultaneous use of forward bulk biasing and an inductor yields a carbon nanotube oscillator with a frequency range of 6‐20 GHz and a phase noise of −123 dBc/Hz. [ABSTRACT FROM AUTHOR]

We report a charge-based analytic and explicit compact model for field-effect transistors (FETs) based on 2-D materials (2DMs), for the simulation of 2DM-based analog and digital circuits. The device electrostatics is handled by invoking 2-D density of states and Fermi–Dirac statistics that are later combined with the Lambert-W function and Halley’s correction to eventually obtain explicit expressions for the electron and hole charges, which are exploited in the calculation of drift-diffusion currents for both carriers. Furthermore, the charge model is extended to obtain characteristics of 2DM-based negative capacitance FETs. The model is benchmarked against experimental MoS2 FET measurements and experimental ambipolar characteristics of narrowband-gap materials, such as black phosphorus. Its soundness for SPICE circuit-level simulations is also demonstrated. [ABSTRACT FROM AUTHOR]

This paper presents a wide frequency range three-stage voltage-controlled ring oscillator in CNTFET technology. The advantages of CNTFETs are the high speed of charge carriers, high signal to noise ratio, small size and ballistic transport. Therefore in comparison with MOSFETs, they have a higher frequency, and can operate at a wide frequency range with a very low phase noise if forward bulk bias and active inductor techniques are simultaneously used in the oscillators that employ CNTFETs. In this paper, the Stanford CNTFET model is implemented in Verilog-A, and the proposed CNT ring oscillator is simulated using ADS software over the 50–500 GHz frequency range. The phase noise of the oscillator is − 136 dBc/Hz at 1 MHz offset, which is suitable for PLL applications. [ABSTRACT FROM AUTHOR]

Resistive Random Access Memories (RRAM) have recently shown outstanding characteristics such as high-scalability, high-speed, high-density, and low-energy operation. A simple and accurate model is crucial for rapid design and verification when using RRAM devices at the circuit level. The appropriate model selection gives insight into the behavior of RRAM as well as the efficient use of its unique properties. This work intends to guide the circuit designers in selecting the most appropriate RRAM model for their applications. We introduce a complete set of evaluation criteria for memristor models: type of model, type of switching, genericity, complexity, compatibility with actual physical switching mechanisms, linearity, symmetry, voltage/current control, hard set/soft reset, support electroforming, support for high programming signal frequencies, existence of a threshold, voltage level, timing dependence, temperature dependence and variability. This study compares the main existing RRAM models and summarizes the results in a table showing the main features and limitations of each model. Through extensive simulations and comparisons with experimental data, we provide an analysis and a validation of the reviewed models within the same simulation environment, ranging from individual elementary cells to large memory arrays. Furthermore, we provide a single and unique Verilog-A code integrating all the compared models.

This paper proposes augmented neural networks (AugNNs) for modeling the behavior of steady-state oscillators in time-domain. Multi-output AugNNs with the corresponding gradient scheme and training methodology are proposed for the modeling of multi-phase oscillators. Using the proposed AugNNs, a novel technique is presented for the modeling of voltage-controlled oscillators (VCOs) including I/O behavior. In the proposed AugNNs, a periodic unit is introduced to capture the relation between the instantaneous frequency and the control signal, and to provide the phase information of the oscillation, which is used to predict the oscillatory output waveforms using feed forward neural networks (FFNN). For the modeling of VCOs including output buffers, an AugNN-based model is proposed, where recurrent neural networks (RNNs) are used to capture the nonlinear dynamic current-voltage relation at the output port. The simulated data of transistor-level oscillator circuit are used to train the proposed model. As a black-box approach, the proposed model protects intellectual property (IP) and can be implemented in Verilog-A. The examples using transistor-level oscillator circuits demonstrate the effectiveness of the proposed model for time-domain analysis.

Summary: Energy is a global demand nowadays. Researchers and Scientists are trying every day to find new resources to generate energy. Mechanical energy is considered one of the most essential energy resources in the world. It can be easily generated and transferred into electrical energy. There are a lot of new technologies that are working to develop small and portable energy harvesters for electronic devices such as piezoelectric and triboelectric nanogenerators (TENGs). However, TENGs are more favorable to piezoelectric nanogenerators due to the availability of nontoxic materials. Moreover, they are cheap and exhibit high performance. This article investigates one of the TENG devices, Zigzag structure. It presents an analytical derivation for the model that addresses all aspects of the TENG such as the output voltage, the output current, the capacitance, the resistive load, the capacitive load and the harvested power step by step. The analytical derivation is also verified using COMSOL simulations to validate the results. The mismatch between the analytical derivation and COMSOL is 0.022% in the open circuit voltage and 0.33% in short circuit charge. Electrical behavior is presented afterwards using Verilog‐A in Cadence to examine the performance of the TENG devices in real life situations. For the chosen parameters, the device delivers a maximum voltage of 23 KV at nearly 90° and a maximum current of 7.5 μA at nearly 10°. The maximum reported output power for a load of 5 GΩ is 5.2 mW. [ABSTRACT FROM AUTHOR]

Advancements in adiabatic quantum computing have enabled a rapid development in thermodynamically reversible logic circuits, which can reduce energy wastage to almost negligible levels. Various reversible logic gates using silicene-based multiplexer logic devices (SMLDs) are designed and demonstrated herein using Verilog-A, then validated by SPICE circuit simulations. The results confirm that the various reversible gates correctly implement the corresponding truth tables, thereby validating the use of SMLDs as building blocks for such gates. The SMLD-based reversible logic gate designs enable a reduction in hardware complexity by 76.92–80.64% compared with complementary metal–oxide–semiconductor (CMOS) technology and a 50% reduction in hardware compared with pass transistor logic-based designs, respectively. [ABSTRACT FROM AUTHOR]

Recent researches have indicated that the gate-overlap tunnel FETs (GOTFETs) exhibit double the on-currents I o n and one-tenth the off-currents I o f f than the equally sized MOSFETs at the same technology node, making them ideal candidates for ultra-low-power VLSI applications. This paper presents a complementary GOTFET (CGOT) based dynamic full adder (DFA), which consumes significantly lower power than conventional CMOS DFAs and operates at double the speed of CMOS DFAs. A conventional DFA designed using GOTFETs instead of MOSFETs exhibits 100 ps (40%) lower & 50 ps (30%) lower delays than CMOS DFA. Furthermore, the CGOT DFA consumes merely 2.6 pW of static power, which is 99% (2 orders) lower than the corresponding CMOS DFA., I o n ,. This paper proposes a novel improved DFA circuit design, which mitigates the dynamic power by eliminating redundant switching activity within the DFA circuit,. The proposed modified DFA topology reduces the total power consumption by 25% than the conventional DFA designs at 50% switching activity. The overall power delay product (PDP) reduces to merely 0.9% of the standard CMOS designs. The total power consumption reduces even further with decreasing switching activity, and the improved CGOT DFA consumes 31% lower total power (at 25% switching activity). [ABSTRACT FROM AUTHOR]

This article shows how to properly define modulated flicker noise in Verilog-A compact models, and how a simulator should handle flicker noise for periodic and transient analyses. By considering flicker noise in a simple linear resistor driven by a sinusoidal source, we demonstrate that the absolute value formulation used in most existing Verilog-A flicker noise models is incorrect when the bias applied to the resistor changes sign. Our new method for definition overcomes this problem, in the resistor as well as more sophisticated devices. The generalization of our approach should be adopted for flicker noise, replacing the formulation in existing Verilog-A device models, and it should be used in all new models. Since Verilog-A is the de facto standard language for compact modeling, it is critical that model developers use the correct formulation. [ABSTRACT FROM AUTHOR]

We present a Verilog-A based compact model for the superconductor-insulator-superconductor (SIS) Josephson junction. The model can generate both hysteretic and non-hysteretic current-voltage (I-V) response for the SIS junctions utilizing the Stewart-McCumber parameter. We calibrate our model with different SIS samples and demonstrate accurate matching between the simulated and experimental results. We implement temperature effect on the energy gap and the critical current of the superconductor to explore the dynamic trends in device characteristics. We calculate the junction inductance and energy as functions of junction current and temperature. We simulate the read/write operations of an SIS junction based cryogenic memory cell to illustrate the usability of our model. [ABSTRACT FROM AUTHOR]

This article proposes a bit-time-dependent behavioral model of input–output (I/O) drivers for overclocking simulation. The driver behavior under overclocking conditions is investigated, and the corresponding weighting function response surface is demonstrated. In contrast to the previous approaches that use fixed timing signals extracted under normal operating conditions only, the proposed model addresses the modeling of overclocking behavior by using bit-time-dependent weighting functions (BTDWFs) along with a transition variable. The weighting coefficients can be generated appropriately for different overclocking scenarios. The corresponding model extraction flow is presented. Using the proposed BTDWFs, the driver input signal is processed during run-time by a finite state machine (FSM) algorithm which can be implemented in the widely supported hardware description languages such as Verilog-A. The proposed model is able to capture the driver’s behavior accurately under both normal operation and overclocking conditions. Its fidelity and simulation speedup are validated with modeling examples using commercial driver circuit. [ABSTRACT FROM AUTHOR]

A ring oscillator is an important circuit used to evaluate the performance limits of any digital technology. The advantages of Graphene field effect transistor (GFET) over current CMOS technologies make it a prominent candidate for future high-performance electronics. In this paper, a GFET model is implemented in Verilog-A, and GFET design and analysis of a ring oscillator are performed using advanced design system (ADS) tool. By using GFET ring oscillator, the designed circuit is simulated using a 0.18 µm GFET process in ADS environment. The results show that the power consumption is 9.98 mW, while the VCO generates 24.12 GHz at 1 V. The effect of Graphene channel length variations on the frequency span, power dissipation and phase noise of GFET ring oscillators are studied. The main performance characteristics of the ring oscillator are compared with CMOS technology. It is shown that a GFET ring oscillator gives a higher oscillation frequency and has more power dissipation. [ABSTRACT FROM AUTHOR]

In this work, a surface potential modeling approach has been proposed to model dual gate, bilayer graphene field effect transistor. The equivalent capacitive network of GFET has been improved considering the quantum capacitance effect for each layer and interlayer capacitances. Surface potentials of both layers are determined analytically from equivalent capacitive network. The explicit expression of drain to source current is established from drift-diffusion transport mechanism using the surface potentials of the layers. The drain current characteristics and transfer characteristics of the developed model shows good agreement with the experimental results in literatures. The small signal parameters of intrinsic graphene transistor i.e., output conductance ( g ds ), transconductance ( g m ), gate to drain capacitance ( C gd ) and gate to source capacitance ( C gs ) have been derived and finally, the cut-off frequency is determined for the developed model. The model is compared with reported experimental data using Normalized Root Mean Square Error (NRMSE) metric and it shows less than 1 6 % NRMSE. A Verilog-A code has been developed for this model and a single ended frequency doubler has been designed in Cadence Design environment using this Verilog-A model. [ABSTRACT FROM AUTHOR]

The paper presents a compact simulation program with integrated circuit emphasis (SPICE) model for a 1200V/19A Silicon Carbide power metallic oxide semiconductor field effect transistor (MOSFET). Based on an equivalent circuit topology, the model completely describes the static and dynamic device characteristics which include the MOSFET channel current, the nonlinear junction capacitance and the switching behavior. Especially the parasitic elements effect is also considered and studied during the modeling, testing and simulation. The model parameters are extracted based on the experimental measurement data. For convenience, the model is implemented by Verilog-A description language and embedded in the simulation software – Advanced Design System (ADS). The validity and accuracy of the model are validated by the double pulse test under inductor load. The Verification result shows that the modeling job is correct and available for prediction of the switching performance under different conditions.

This paper introduces an innovative Gate Overlap Tunnel FET (GOTFET) device which is an advanced TFET engineered to yield double the on current I on , while the off current I off remains an order lower than the analogous MOSFET having same width at the same technology node. A conventional Dynamic Comparator designed using the proposed Complementary GOTFET (CGOT) paradigm exhibits 93 ps (25%) lower delay than similar CMOS designs and consumes merely 1.11 pW (99% lower than CMOS) of static power. The overall power delay product (PDP) in the CGOT comparator design has been shown to be only 0.5% of the PDP of a conventional CMOS comparator. Although the advantages of higher I on are manifold, however, it increases dynamic power as well. So this paper goes beyond device-level improvisation and proposes for the first time, a novel improved comparator circuit designed using the CGOT paradigm which further reduces the total power by an additional 44.5%. [ABSTRACT FROM AUTHOR]