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In recent years, 2D/3D heterojunction electronic devices have attracted considerable attention. As the size decreases, enhancing the speed of MOSFETs, reducing the subthreshold swing (SS), and lowering the power consumption (P) have become challenging. Therefore, in the post‐Moore era, in response to the continuation of Moore's law, junction field‐effect transistors (JFETs) based on mixed‐dimensional MoS2/GaN heterojunctions are proposed via thickness engineering. Accordingly, flat hetero interface and large potential barrier height of 5 eV across the heterojunction, an ultra‐low SS of 60.9 mV dec−1 (The Boltzmann limit is 60 mV dec−1) is achieved at Vds = 0.1 V when the MoS2 thickness is 10 nm. Additionally, a high Ion/Ioff ratio of 107 and a saturation current density (Jds) of 0.16 µA µm−1 is achieved. As the thickness of MoS2 increased from 6 to 16 nm, the working mode transitioned from enhancement mode to depletion mode. The depletion region across the channel is verified using computer‐aided design technology. Finally, an N‐type load inverter with a maximum voltage gain of 4 and a minimum static P of 25 nW is applied. Overall, the work provides a universal strategy for constructing a series of high‐performance transition metal dichalcogenide/GaN JFETs. [ABSTRACT FROM AUTHOR]

High-k dielectric insulators are required to reduce leakage and increase transistor performance. They are able to impact the mobility of carriers in transistors positively, leading to better device performance in advanced transistor architecture. Nevertheless, an in-depth analysis of how high-k dielectric insulators influence transistor characteristics must be carried out to determine their suitability. The objective of this study is to investigate the impact of high-k insulators towards electrical properties of junctionless double gate strained transistor. The simulation works is done using process/device simulator Silvaco Athena/Atlas. Based on the retrieved results, the magnitude of ION, on-off ratio, gm, and Cint for TiO2-based device are approximately 63%, 99%, 62%, and 89% respectively higher than the lowest permittivity materialbased device. The TiO2-based device also exhibits the lowest magnitude in IOFF and SS compared to others. However, a significant degradation in fT magnitude have been observed for TiO2-based device significantly due to its large capacitances. [ABSTRACT FROM AUTHOR]

We report here a study on doping concentration variation on Double Gate Junctionless Field Effect Transistor. Doping concentration for the device is varied from 1010/cm³ to 1019/cm³ and their transfer characteristics and output characteristics were investigated for drain section voltages with 0.1 V, 0.5 V and 1 V. At 1 V drain voltage with doping level 1019 cm-3 a drain current of 1.7 mA has been obtained. Furthermore various electrical parameters like on current, Ion to Iorr ratio, subthreshold swing, threshold voltages are investigated. At 1019 cm and drain potential 1 V current in body is 1.9 mA. On the other hand subthreshold swing obtained at 1019 cm with a drain potential 1 V is 79 mV/Decade. The simulation is done with the help of Cogenda Visual TCAD simulator. By increasing doping concentration better control over drain current can be obtained. Better on current can be achieved at higher doping variation. [ABSTRACT FROM AUTHOR]

Abstract The growth of two-dimensional hexagonal aluminum nitride (h-AlN) on transition metal dichalcogenide (TMD) monolayers exhibits superior uniformity and smoothness compared to HfO $$_{2}$$ 2 on silicon substrate. This makes an h-AlN monolayer an ideal spacer between the gate oxide material and the WSe2 monolayer in a two-dimensional field effect transistor (FET). From first principles approaches, we calculate and compare the transmission functions and current densities of Pt–WSe2–Pt nanojunctions without and with the insertion of an h-AlN monolayer as a spacer in the gate architecture. The inclusion of h-AlN can alter the characteristics of the Pt–WSe2–Pt FET in response to the gate voltage ( $$V_\text {g}$$ V g ). The FET without (or with) h-AlN exhibits the characteristics of a P-type (or bipolar) transistor: an on/off ratio of around $$2.5 \times 10^{6}$$ 2.5 × 10 6 (or $$1.7 \times 10^{6}$$ 1.7 × 10 6 ); and an average subthreshold swing (S.S.) of approximately 109 mV/ $$\text {dec.}$$ dec. (or 112 mV/ $$\text {dec.}$$ dec. ), respectively. We observe that $$V_\text {g}$$ V g shifts the profile of the transmission function by an energy of $$\alpha (e V_{\text {g}})$$ α ( e V g ) , where $$\alpha$$ α represents the gate-controlling efficiency. We observed that $$\alpha _{\text {in}}=83\%$$ α in = 83 % and $$\alpha _{\text {out}}=33\%$$ α out = 33 % , corresponding to whether the Fermi energy is located inside or outside the band gap. Therefore, we construct an effective gate model based on the Landauer formula, with the transmission function at $$V_\text {g}=0$$ V g = 0 as the baseline. Our model generates results that are consistent with those obtained through first principles calculations. The relative error in current densities between model and first-principles calculations is within $$[\frac{ln(10)}{S.S.}] | \Delta V_{\text {G}}^{\text {eff}} |$$ [ l n ( 10 ) S . S . ] | Δ V G eff | . The 2D atomistic FETs show excellent device specifications and the ability to compete with existing transistors based on traditional silicon technology. Our findings could help advance the design of TMD-based FETs.

Implantable medical devices have revolutionized healthcare by providing continuous monitoring and therapeutic interventions within the human body. The overall performance of these devices is heavily dependent on the effectiveness and efficiency of integrated electronic components, such as transistors. This survey explores the growing utilization of Tunnel Field-Effect Transistors (TFETs) in implantable devices, shedding light on their advantages and challenges in this specific application domain. TFETs, characterized by their unique tunnelling mechanism, offer several advantages that make them well suited for implantable devices. Their low-power consumption, reduced leakage current, and improved subthreshold swing make them ideal for energy-efficient, long-lasting operation within the constrained power budgets of implantable devices. Furthermore, TFETs exhibit excellent performance at low supply voltages, ensuring minimal tissue damage and heat generation. This survey also addresses the challenges associated with TFETs in implantable devices, including fabrication complexities, variability, and compatibility with existing technologies. It highlights recent advancements in TFET technology that address these concerns, such as improved material choices and manufacturing techniques. As technology continues to advance, TFETs are poised to play a pivotal role in improving the overall efficiency and reliability of life-saving technologies and medical devices. Overall, this survey provides valuable insights into the current state and future prospects of TFETs in implantable devices, guiding researchers and engineers in harnessing their potential for the benefit of healthcare and patient well-being. [ABSTRACT FROM AUTHOR]

The pursuit of near‐ideal subthreshold swing (SS) ≈ 60 mV dec−1 is a primary driving force to realize the power‐efficient field‐effect transistors (FETs). This challenge is particularly pronounced in 2D material‐based FETs, where the presence of a large interface trap density (Dit) imposes limitations on electrostatic control, consequently escalating power consumption. In this study, the gate controllability of 2D FETs is systematically analyzed by fabricating pre‐patterned van der Waals (vdW)‐contacted p‐FETs, varying the WSe2 channel thickness from monolayer to ten‐layer. As a result, the channel thickness is optimized to achieve efficient gate controllability while minimizing Dit. The findings demonstrate negligible hysteresis and excellent subthreshold swing (SSmin) close to the thermal limit (≈60 mV dec−1), with a corresponding Dit of ≈1010 cm−2 eV−1, comparable to Dit values observed in state‐of‐the‐art Si transistors, when utilizing WSe2 channel thicknesses ≥ five‐layer. However, reducing the WSe2 channel thickness below the trilayer, SSmin (≈91 mV dec−1) deviates from the thermal limit, attributed to a comparatively higher Dit (≈1011 cm−2 eV−1), despite the still lower than values reported for surface‐contacted 2D transistors. Furthermore, all devices exhibit consistent p‐type characteristics, featuring a high ION/IOFF ratio, high mobility, and excellent electrical stability confirmed over several months. [ABSTRACT FROM AUTHOR]

In this paper, a new stacked gate oxide L-shaped Tunnel Field Effect Transistor (LTFET) is proposed. The stacked gate oxide structure incorporates high-k and SiO2 dielectrics. The high-k dielectric, specifically, contributes to a robust electric field at the source/channel junction. This augmented electric field results in more energy band bending and a thinner tunneling barrier. As a result, the proposed device shows the drain current of 0.224 mA/μm, OFF-current of 1.3 × 10–17 A/μm, threshold voltage of 0.62 V and average subthreshold swing of 34 mV/decade, in comparison with the conventional LTFET. Moreover, this paper demonstrates the role of both Shockley–Read–Hall generation and trap assisted tunneling in the subthreshold swing degradation due to the existence of trap inside the silicon band gap. [ABSTRACT FROM AUTHOR]

The progress in semiconductor technology has played a crucial role in enhancing human existence by introducing significant innovations. The pursuit of high-performance devices utilizing novel materials has emerged as a crucial avenue for surmounting the existing limitations of silicon-based technologies. This paper presents an evaluation of the diverse short channel effects (SCEs) exhibited by the double gate n-FinFET structure, considering the influence of temperature on channel materials using metal gate (MG) as Gallium Arsenide (GaAs) alongside High-K dielectric oxide materials such as Hafnium Oxide (HfO2), Lanthanum Oxide (La2O3) and Lanthanum Aluminum Oxide (LaAlO3) in comparison with traditional Silicon Dioxide (SiO2). The investigation and presentation of the impact of gate length (Lg), channel width (Wch), doping, and varying Temperature (275k-450k) on several short channel effects (SCEs), namely Drain Induced Barrier Lowering (DIBL), Subthreshold Slope (SS), threshold voltage (Vth) roll-off, Transconductance (gm) and ON-OFF current ratio (ION / IOFF) have been thoroughly examined using the aforementioned materials. The utilization of FinFET technology using HK-MG presents notable benefits in terms of mitigating the subthreshold swing while concurrently maintaining a low drain-induced barrier lowering (DIBL) effect. [ABSTRACT FROM AUTHOR]

Tunnel field effect transistors (TFETs) are known for lower power requirements than MOSFETs due to their utilization of the band-to-band tunneling mechanism, along with low subthreshold swing (SS). The traditional TFET suffers from low drain current; however, drain current can be improved by modifying the TFET device structure. In this work, a 2-D heterojunction (Ge/Si) vertical-tunnel field effect transistor (HV-TFET) with an optimal design is proposed in which the source region is made of germanium (Ge) due to its low bandgap, while silicon (Si) is used for the regions of drain and channel to mitigate leakage current because of its wider bandgap. The goal of this work is to achieve improved switching by enhancing the ON-state current (ION) and reducing the OFF-state current (IOFF). The currents obtained have values of 1.19 × 10−3 A/µm and ~ 10−15 A/µm, respectively, and therefore the ION/IOFF ratio is ~ 1011 for the device proposed in this paper. Three different dielectric gate oxide materials are used for studying the effect of dielectric materials on the device parameters. Hafnium oxide (HfO2) is found to offer the best results when used for gate oxide, and hence is used in the proposed device structure. Also, this work examines a number of electrical parameters of the device structure due to changes in physical device parameters. The results are produced using the Sentaurus TCAD tool to confirm the suitability of the proposed device for use in circuit applications with low-power strategies. [ABSTRACT FROM AUTHOR]

The present study proposes an approach to enhance the DC and RF performance parameters of a double-gate tunnel field-effect transistor (DGTFET). The approach integrates an extended source with stacked drain layers of varying doping concentrations. This integration results in a drain-engineered extended source double-gate tunnel FET (DE-ES-DGTFET), demonstrating low ambipolarity and abrupt switching. The source and drain engineering enable the device to increase the ON-current while simultaneously reducing ambipolarity due to the large tunneling area with different drain doping concentrations. The optimization of the device's performance parameters was carried out by varying the doping concentration of the stacked drain, source length, and thickness of the drain. The proposed device achieved significant improvements compared to conventional DGTFETs, including a two-decade reduction in ambipolar current, an order of improvement in the ON-current (ION) of ~ 10−5 A/µm, two orders of reduction in ambipolarity (IAmb) 5.91 × 10−17 A/µm, two orders of enhancement in ratio ION/IOFF of − 1013, a subthreshold swing (SS) of 23.3 mV/dec, and nearly a two-fold increase in cut-off frequency (fT), and a transit time (τ ) ~ 80 ps have been accomplished. [ABSTRACT FROM AUTHOR]

This article presents a study on the subthreshold swing (SS) and the ON–OFF current ratio of a negative capacitance source pocket double-gate tunnel field-effect transistor (NC-SP-DGTFET). In this analysis, a novel device is developed that integrates gate and channel engineering techniques. The combination of the ferroelectric material hafnium zirconium oxide (HZO) with the dielectric material SiO2 generates a negative capacitance (NC) effect. Additionally, the incorporation of a totally depleted source pocket into the DGTFET reduces the tunneling width. The addition of NC has the potential to improve the SS through the amplification of the electric field at the tunnel junction. Moreover, it has been observed that a fully depleted source pocket within the source/channel region significantly enhances the ION current when compared to the double-gate tunnel field-effect transistor (DGTFET). Following thorough device optimization, there has been a notable enhancement in the ION/IOFF current ratio, SS, and transconductance (gm) by a factor of 1.54 × 1013, 20.8 mV/dec, and 5.102 × 10−4 S/µm, respectively. These improvements signify superior energy efficiency and enhanced performance when compared to both DGTFET and source pocket based DGTFET (SP-DGTFET) configurations. Furthermore, substantial research has been conducted on the variation in electrical properties in relation to the thickness of ferroelectric materials. The findings indicate that the proposed device exhibits considerable potential as a viable option for applications requiring both low power consumption and high operational speed. [ABSTRACT FROM AUTHOR]

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Abstract The pursuit of near‐ideal subthreshold swing (SS) ≈ 60 mV dec−1 is a primary driving force to realize the power‐efficient field‐effect transistors (FETs). This challenge is particularly pronounced in 2D material‐based FETs, where the presence of a large interface trap density (Dit) imposes limitations on electrostatic control, consequently escalating power consumption. In this study, the gate controllability of 2D FETs is systematically analyzed by fabricating pre‐patterned van der Waals (vdW)‐contacted p‐FETs, varying the WSe2 channel thickness from monolayer to ten‐layer. As a result, the channel thickness is optimized to achieve efficient gate controllability while minimizing Dit. The findings demonstrate negligible hysteresis and excellent subthreshold swing (SSmin) close to the thermal limit (≈60 mV dec−1), with a corresponding Dit of ≈1010 cm−2 eV−1, comparable to Dit values observed in state‐of‐the‐art Si transistors, when utilizing WSe2 channel thicknesses ≥ five‐layer. However, reducing the WSe2 channel thickness below the trilayer, SSmin (≈91 mV dec−1) deviates from the thermal limit, attributed to a comparatively higher Dit (≈1011 cm−2 eV−1), despite the still lower than values reported for surface‐contacted 2D transistors. Furthermore, all devices exhibit consistent p‐type characteristics, featuring a high ION/IOFF ratio, high mobility, and excellent electrical stability confirmed over several months.

An analytical subthreshold swing (SS) model has been presented to determine the SS of an elliptic junctionless gate-all-around field-effect transistor (GAA FET). The analysis of a GAA FET with an elliptic cross-section is essential because it is difficult to manufacture a GAA FET with an accurate circular cross-section during the process. The SS values obtained using the proposed SS model were compared with 2D simulation values and other papers to confirm good agreement. Using this analytical SS model, SS was analyzed according to the eccentricity of the elliptic cross-section structure. As a result, it was found that the carrier control ability within the channel improved as the eccentricity increased due to a decrease in the effective channel radius by a decrease in the minor axis length and a decrease in the minimum potential distribution within the channel, and thus the SS decreased. There was no significant change in SS until the eccentricity increased to 0.75 corresponding to the aspect ratio (AR), the ratio of the minor and major axis lengths, of 1.5. However, SS significantly decreased when the eccentricity increased to 0.87 corresponding to AR = 2. As a result of the SS analysis for changes in the device parameters of the GAA FET, changes in the channel length, radius, and oxide film thickness significantly affected the changing rate of SS with eccentricity.

This study explores the optimization of a hetero-dielectric tunnel field-effect transistor (HDTFET) structure to improve device performance. By incorporating a high-k oxide pocket in a portion of the source-side gate insulator, a local minimum in the conduction band edge is induced at the source-channel interface. This technique leads to improved tunneling rates and increased current handling capability. The simulation analysis focuses on optimizing the position and dimension of the high-k dielectric pocket to enhance key device characterization metrics such as ON-state current (ION), ON-to-OFF-state current ratio (ION/IOFF), subthreshold swing (SS), and cutoff frequency (fT). The resulting optimized design for a 30 nm-channel length involves a pocket shift of 1 nm and a pocket length of 12 nm. This configuration achieves a remarkable ON current of 55 µA/µm, which is 30 times higher than that of a conventional TFET. Importantly, other analog performance parameters remain unaffected, with fT surpassing 175 GHz for the 30 nm-channel. Additionally, transient analysis is conducted by applying a resistive load inverter circuit to a pulse input. The fall propagation delay (tphl) exhibits a greater than two orders of magnitude enhancement, along with improved overshoot voltage (VP) compared to a TFET without a pocket. The study further explores the impact of supply scaling on transient parameters. Optimal pocket scalability concerning channel length is found to be 40% for pocket length and approximately 2.5% for pocket shift relative to the source-channel interface. The proposed design significantly enhances DC and analog as well as circuit-level metrics compared to the traditional uniform gate oxide TFET.

This study introduces a novel double-dielectric Si/GaSb heterojunction TFET, incorporating III-V material in the pockets and source region to enhance band-to-band tunneling. Utilizing a high- κ dielectric in conjunction with S i O 2 as a gate oxide, the proposed TFET demonstrates notable advancements, including an 81% reduction in OFF-current and a substantial 1.58-decade enhancement in ON-current. However, a moderate 30% increase in the average subthreshold swing is observed compared to the referenced pocket-based GaSb/Si VTFET. The RF characteristics reveal a significant 1.62-decade increase in transconductance and a 1.8-decade increase in output conductance, coupled with impressive cut-off frequency and gain-bandwidth product relative to the same reference. Additionally, the study implements a 7T SRAM cell at the device-to-circuit level through a lookup table-based Verilog-A methodology. It showcases higher noise margins and lower delays, rendering it suitable for ultra-low voltage applications requiring high-speed performance and enhanced stability. [ABSTRACT FROM AUTHOR]

This paper proposes a compact model for a top-gated negative capacitance-based carbon nanotube field-effect transistor (NC-CNTFET). The proposed model relies on a metal–ferroelectric–metal–insulator–semiconductor (MFMIS) configuration. A charge-based modelling approach is used for the top-gated CNTFET, where the surface charge of the CNT is calculated from chirality and gate bias. This charge is the same as the NC-CNTFET device's total charge, based on which the compact model for the proposed device is developed. The ferroelectric material of choice is hafnium silicon oxide (HfSiO). A comparison of the NC-CNTFET with the top-gated CNTFET (TG-CNTFET) is also shown. The results show an improved subthreshold slope and ON/OFF-current ratio in the NC-CNTFET because of the negative capacitance effect of the ferroelectric layer. The impact of different ferroelectric thicknesses is also shown, which suggests further improvement in device performance as the ferroelectric thickness increases. [ABSTRACT FROM AUTHOR]

This study explores the optimization of a hetero-dielectric tunnel field-effect transistor (HDTFET) structure to improve device performance. By incorporating a high-k oxide pocket in a portion of the source-side gate insulator, a local minimum in the conduction band edge is induced at the source-channel interface. This technique leads to improved tunneling rates and increased current handling capability. The simulation analysis focuses on optimizing the position and dimension of the high-k dielectric pocket to enhance key device characterization metrics such as ON-state current (I ON), ON-to-OFF-state current ratio (I ON / I OFF), subthreshold swing (SS), and cutoff frequency (f T). The resulting optimized design for a 30 nm-channel length involves a pocket shift of 1 nm and a pocket length of 12 nm. This configuration achieves a remarkable ON current of 55 µA/µm, which is 30 times higher than that of a conventional TFET. Importantly, other analog performance parameters remain unaffected, with f T surpassing 175 GHz for the 30 nm-channel. Additionally, transient analysis is conducted by applying a resistive load inverter circuit to a pulse input. The fall propagation delay (t phl) exhibits a greater than two orders of magnitude enhancement, along with improved overshoot voltage (V P) compared to a TFET without a pocket. The study further explores the impact of supply scaling on transient parameters. Optimal pocket scalability concerning channel length is found to be 40% for pocket length and approximately 2.5% for pocket shift relative to the source-channel interface. The proposed design significantly enhances DC and analog as well as circuit-level metrics compared to the traditional uniform gate oxide TFET. [ABSTRACT FROM AUTHOR]

FinFETs ensured the continuation of semiconductor industry with reliable, high performance and low power devices fabricated at sub-100 nm technology nodes. These FinFETs are able to suppress the Short Channel Effects quite effectively while decreasing the leakage currents. Below 22 nm gate lengths, the SCEs resurfaced. To suppress these effects, the thickness of the gate oxide reduced. As the gate oxide thickness reached below 2 nm, the leakage currents started increasing again. Thus arose the need for replacing SiO2 with high permittivity dielectric materials like Zirconium Dioxide, Hafnium Oxide, Aluminum Oxide and Silicon Nitrate. Research also suggested the use of Multi Fin architectures to enhance the drain currents. The focus of this paper is to develop multiple fin 08 nm gate length SOI FinFETs having three fin architecture where the gate oxide of each fin consists of a stacked combination of 0.5 nm of high-k dielectrics atop another layer of 0.5 nm of SiO2 to reduce the leakage currents and other SCEs. The use of 3-Fin structures significantly enhances the drain current leading to higher switching speeds for faster CMOS fabrication and optimized device performance towards semiconductor industry. [ABSTRACT FROM AUTHOR]

In this paper, the sensitivity of a dielectric-modulated split-drain Z-shaped gate tunnel field-effect transistor (DM-SDZ-TFET) is investigated for label-free detection of biomolecules using the drain engineering approach. The threshold voltage (Vth), on-current (Ion), switching current ratio (Ion/Ioff), and subthreshold swing (SS) characteristics are used in the in-depth investigation of the sensitivity of the device. The drain engineering strategy is very effective in reducing the ambipolar current as well as the leakage current of the device, and it increases the Ion/Ioff current ratio. The sensitivity of this biosensor was explored comprehensively with extensive simulation by addressing concerns with both drain doping variations and the practical binding difficulties of the biomolecules in the cavity area. The influence of biomolecule position and occupancy rate on device sensitivity was analyzed in detail using three distinct scenarios. The device also demonstrated a high Ion of 10−4 A/µm for the dielectric constant of biomolecules K = 12 (gelatin). This biosensor shows high switching current ratio sensitivity (SIon/Ioff) of 1.5 × 104 and threshold sensitivity of 0.245 for the K = 12 target biomolecule. A comparative study reveals that the proposed biosensor provides better sensitivity performance with respect to all possible sensitivity parameters and superior biomolecule detection when compared with the ZHP-DM-TFET biosensor. The simulations of the device are performed using the Silvaco TCAD tool. [ABSTRACT FROM AUTHOR]

While gate workfunction fluctuation causes the threshold voltage shift of transistors, it leads to off- and on-state current variations with a given supply voltage and circuit performance degradation at room temperatures. However, the impacts of gate workfunction fluctuation on device electrical characteristics at cryogenic temperatures are still unclear yet. Based on self-consistent numerical simulations, we report in this work that cryogenic operation of n-channel transistors magnifies the influence of gate granularity on the device performance variation in terms of threshold voltage, subthreshold swing and drain currents. Gate granularity roughens the channel potential landscape and forms the local minima on the conduction band for electron transport, and which effectively reduces the device channel width. Our results highlight current deterioration in the subthreshold and weak inversion regions at cryogenic temperatures due to gate granularity. It may result in subthreshold swing saturation at cryogenic temperatures and pose a challenge to supply voltage scaling for power management. Device physics is explained and potential solution is discussed in this paper.

We demonstrate that the shorter channel self-aligned top-gate (SA TG) coplanar indiumgallium- zinc oxide (IGZO) thin-film transistors (TFTs), with negative voltage applied to the back-gate, exhibit superior characteristics as driving transistors in organic light-emitting diode (OLED) pixels compared to their longer channel counterparts. The shorter channel IGZO TFTs (with a channel length (L) of 3 μm) biased with a back gate voltage of −3.5 V showed a larger subthreshold swing (SS = 0.21 V/dec) than the longer channel ones (with L = 5 μm, SS = 0.16 V/dec) with a similar threshold value (VTH = 0.7–0.8 V). A large SS is beneficial for controlling grayscale levels, especially at low gray levels, when IGZO TFTs are used as driving transistors in OLED pixels. Furthermore, the negatively back-gate-biased shorter channel SA TG coplanar IGZO TFTs exhibited significantly enhanced electrical stability compared to the longer channel ones under both positive gate bias and hot carrier stresses. The findings of this study are expected to be useful in expanding the utility of IGZO TFTs in OLED displays.

We reported the fabrication of indium‐gallium‐zinc oxide (IGZO) thin‐film transistors (TFTs) by plasma‐enhanced atomic‐layer‐deposition (PEALD) process using different surface reactivities of the precursor‐substrate combinations with controlled deposition sequences. In‐Zn‐Ga (Case II) exhibited favorable subthreshold swing (SS) values of 313 mV/decade, and moderate mobility (µFE) of 29.3 cm2/Vs compared to In‐Ga‐Zn (Case I) (84 mV/decade and 33.4 cm2/Vs). [ABSTRACT FROM AUTHOR]

An analytical SS model is presented to observe the subthreshold swing (SS) of a junctionless gate-all-around (GAA) FET with ferroelectric in this paper. For the gate structure, a multilayer structure of metal-ferroelectric-metal-insulator-semiconductor (MFMIS) was used, and the SS was calculated in $15 \leqslant {P_r} \leqslant 30\,\mu C/c{m^2}$ and $0.8 \leqslant {E_c} \leqslant 1.5\,MV/cm$, which are the ranges of remanent polarization and coercive field suggested in various experiments in the case of HZO as the ferroelectric material. It was found that the SSs from the presented analytical SS model agree well with those derived from the relationship between drain current and gate voltage using a 2D potential distribution in the range of device parameters used for simulation. As a result of analyzing the SS of the junctionless GAA FET with ferroelectric using the analytical SS model presented in this paper, the SS decreased because the voltage across the inner gate decreased when the ferroelectric thickness increased. It was observed that the condition of SS < 60 mV/dec was sufficiently obtained according to changes in device parameters such as channel length, channel radius and ferroelectric thickness, and that the SS maintained a constant value according to the ratio of remanent polarization and coercive field Pr/Ec. As Pr/Ec increases, the SS increases as the ferroelectric capacitance increases. As the channel length becomes smaller, the change in SS according to Pr/Ec is more severe.

Abstract In this paper, we propose an inductive line tunneling FET using Epitaxial Tunnel Layer with Ge-Source and Charge Enhancement Insulation (CEI ETL GS-iTFET). The CEI ETL GS-iTFET allows full overlap between the gate and source regions, thereby enhancing the line tunneling. In addition, a germanium layer is introduced on the source side to form a heterojunction, effectively improving the device's conduction current. An ETL is incorporated to combat point tunneling leakage, resulting in a steeper subthreshold swing. Furthermore, a CEI consisting of Si3N4 is introduced between the germanium source and the Schottky metal, which effectively reduces carrier losses in the inversion layer and improves the overall device performance. This study presents a calibration-based approach to simulations, taking into account practical process considerations. Simulation results show that at V D = 0.2 V, the CEI ETL GS-iTFET achieves an average subthreshold swing (SS avg) of 30.5 mV/dec, an I on of 3.12 × 10–5 A/μm and an I on/I off ratio of 1.81 × 1010. These results demonstrate a significantly low subthreshold swing and a high current ratio of about 1010. In addition, the proposed device eliminates the need for multiple implantation processes, resulting in significant manufacturing cost reductions. As a result, the CEI ETL GS-iTFET shows remarkable potential in future low-power device competition.

The tunneling field effect transistor (TFET) is a viable candidate for designing a highly sensitive biosensor. In this work, a doping-less Z-shaped dielectrically modulated charge plasma TFET (CPTFET) structure with misaligned cavity region on channel and source has been proposed for label-free biosensing applications. To design the device, charge plasma technique has been employed, where appropriate metal workfunction is used over intrinsic silicon to create n + drain and p + source regions. The charge plasma approach reduces thermal budget, random dopant fluctuation (RDF) and steps required for fabrication. The Z-shaped CPTFET includes the advantage of abrupt profile of doping at source-channel (tunneling) junction. Because cavities are created in source and gate oxide region, the abrupt doping profile suppresses ambipolar behavior and improves sensitivity. The performance of the proposed device for both charged and neutral biomolecules in terms of electric field, band energy, transfer characteristics, I ON / I OFF ratio and subthreshold swing (SS) has been examined. The response of other parameters like cavity thickness and cavity length on ON current has been analyzed using the Silvaco ATLAS device simulator. [ABSTRACT FROM AUTHOR]

We report a computational study on the possibility of designing nanoscale organic tunnel field-effect transistors (OTFETs) with a subthreshold swing (SS) much smaller than 60 mV/dec and on-state current (Ion) much larger than that of conventional organic field-effect transistors. The OTFETs are designed on the basis of two-dimensional metallophthalocyanine covalent-organic frameworks (2D MPc-COFs) by employing first-principles and quantum-transport approaches in the ballistic-transport regime. The designed OTFETs with architecture of the van der Waals heterojunction manifest themselves with SS as small as 21 mV/dec and Ion as large as 887.5 μA/μm. These devices outperform most tunnel field-effect transistors reported in the literature and fulfill the IRDS (International Roadmap for Devices and Systems) requirement for both high-performance (HP) and low-power (LP) devices. We reveal that 2D MPc-COFs with moderate band gaps are highly required to optimize the device performance. This study provides an insight into the promising application of 2D COFs beyond conventional organic materials in the rational design of HP and LP nanoscale OTFETs. [ABSTRACT FROM AUTHOR]

A novel hybrid double gate junctionless transistor with gate engineering using a dual gate oxide stack has been proposed to improve short-channel effects and gate controllability for digital applications. The performance analysis and comparison of the proposed device with a DGLK junctionless transistor has been reported, hybrid Junctionless double gate transistor device has provided SS 61.4 mV/decade which is close to the ideal value of 60 mV/decade and 27.91% improvement, DIBL of 7.368 mV/V with 88.487% improvement, off current is 35.6 fA/µm, which is nearly 1.6 x10-6 times less and very high switching ratio of 1.648x 1010 which is 5.455 x106 times higher than junctionless double gate transistor. Also, the effect of variations in gate dielectric, spacer length has been studied. [ABSTRACT FROM AUTHOR]

A semiconductor/dielectric interface is one of the dominant factors in device characteristics, and a variety of oxides with high dielectric constants and low interface trap densities have been used in carbon nanotube transistors. Given the crystal structure of nanotubes with no dangling bonds, there remains room to investigate unconventional dielectric materials. Here, we fabricate carbon nanotube transistors with boron nitride nanotubes as interfacial layers between channels and gate dielectrics, where a single semiconducting nanotube is used to focus on switching behaviors at the subthreshold regime. The subthreshold swing of 68 mV·dec−1 is obtained despite a 100-nm-thick SiO2 dielectric, corresponding to the effective interface trap density of 5.2 × 1011 cm−2·eV−1, one order of magnitude lower than those of carbon nanotube devices without boron nitride passivation. The interfacial layers also result in the mild suppression of threshold voltage variation and hysteresis. We achieve Ohmic contacts through the selective etching of boron nitride nanotubes with XeF2 gas, overcoming the trade-off imposed by wrapping the inner nanotubes. Negligible impacts of fluorinating carbon nanotubes on device performances are also confirmed as long as the etching is applied exclusively at source/drain regions. Our results represent an important step toward nanoelectronics that exploit the advantage of one-dimensional van der Waals heterostructures. [ABSTRACT FROM AUTHOR]

Abstract This article presents a new line tunneling dominating metal–semiconductor contact-induced SiGe–Si tunnel field-effect transistor with control gate (CG-Line SiGe/Si iTFET). With a structure where two symmetrical control gates at the drain region are given a sufficient negative bias, the overlap of the energy bands at the drain in the OFF-state is effectively suppressed, thus reducing the tunneling probability and significantly decreasing leakage current. Additionally, the large overlap area between the source and gate improves the gate’s ability to control the tunneling interface effectively, improving the ON-state current and subthreshold swing characteristics. By using the Schottky contact characteristics of a metal–semiconductor contact with different work functions to form a PN junction, the need to control doping profiles or random doping fluctuations is avoided. Furthermore, as ion implantation is not required, issues related to subsequent annealing are also eliminated, greatly reducing thermal budget. Due to the different material bandgap characteristics selected for the source and drain regions, the probability of overlap of the energy bands in the source region in the ON-state is increased and that in the drain region in the OFF-state is reduced. Based on the feasibility of the actual fabrication process and through rigorous 2D simulation studies, improvements in subthreshold swing and high on/off current ratio can be achieved simultaneously based on the proposed device structure. Additionally, the presence of the control gate structure effectively suppresses leakage current, further enhancing its potential for low-power-consumption applications.

Abstract In this article, a new p+ pocket stacked gate oxide junctionless tunnelling field effect transistor (junction less tunnelling field effect transistor (JLTFET)) which has metal strip in gate oxide layer is proposed for analogue/RF circuit applications. Due to the insertion of a p+ pocket in source/channel junction and the use of metal strip in oxide layer, the following properties of the proposed JLTFET are resulted. First, the tunnelling barrier width is reduced in the source/channel junction thereby, electrons easily tunnel from the source to the channel. Second, the hole concentration (empty state) in the channel is increased, leading to higher electron contribution in the tunnelling process. These improvements are useful in achieving high drain current and steep subthreshold swing. As a result, the maximum ON current of 4.4 × 10−5 A/μm and average subthreshold swing of 40 mV/decade are obtained from simulation results. Moreover, as compared to conventional JLTFET, the proposed JLTFET provides improvements in reliability and analogue/radio frequency (RF) performance.

The single‐molecule electronic devices offer the ultimate solution to miniaturize integrated circuits, and subthreshold swing (SS) is the key indicator of the power consumption for single‐molecule transistors but is still quite restricted. In this study, the redox‐mediated single‐molecule transistor with a SS down to 120 mV decade−1 in the faradaic potential region via the electrochemical‐STM break junction (EC‐STM‐BJ) technique is fabricated. With an off‐state leakage current of less than 10 pA and an on/off ratio of 100, the balance between low static power consumption and a high switching ratio is achieved. The theoretical investigations reveal that the conductance tuning is from the difference of transmission in the redox process. The study provides a new strategy for the design of single‐molecule transistors with promising SS, which is essential for the potential application of single‐molecule devices. [ABSTRACT FROM AUTHOR]

The single‐molecule electronic devices offer the ultimate solution to miniaturize integrated circuits, and subthreshold swing (SS) is the key indicator of the power consumption for single‐molecule transistors but is still quite restricted. In this study, the redox‐mediated single‐molecule transistor with a SS down to 120 mV decade−1 in the faradaic potential region via the electrochemical‐STM break junction (EC‐STM‐BJ) technique is fabricated. With an off‐state leakage current of less than 10 pA and an on/off ratio of 100, the balance between low static power consumption and a high switching ratio is achieved. The theoretical investigations reveal that the conductance tuning is from the difference of transmission in the redox process. The study provides a new strategy for the design of single‐molecule transistors with promising SS, which is essential for the potential application of single‐molecule devices. [ABSTRACT FROM AUTHOR]

An analytical SS model is presented to observe the subthreshold swing (SS) of a junctionless gate-all-around (GAA) FET with ferroelectric in this paper. For the gate structure, a multilayer structure of metal-ferroelectric-metal-insulator-semiconductor (MFMIS) was used, and the SS was calculated in 15 ⩽ P r ⩽ 30 μ C / c m 2 and 0.8 ⩽ E c ⩽ 1.5 M V / c m , which are the ranges of remanent polarization and coercive field suggested in various experiments in the case of HZO as the ferroelectric material. It was found that the SSs from the presented analytical SS model agree well with those derived from the relationship between drain current and gate voltage using a 2D potential distribution in the range of device parameters used for simulation. As a result of analyzing the SS of the junctionless GAA FET with ferroelectric using the analytical SS model presented in this paper, the SS decreased because the voltage across the inner gate decreased when the ferroelectric thickness increased. It was observed that the condition of SS < 60 mV/dec was sufficiently obtained according to changes in device parameters such as channel length, channel radius and ferroelectric thickness, and that the SS maintained a constant value according to the ratio of remanent polarization and coercive field P r / E c . As P r / E c increases, the SS increases as the ferroelectric capacitance increases. As the channel length becomes smaller, the change in SS according to P r / E c is more severe. An analytical SS model is presented to observe the subthreshold swing (SS) of a junctionless gate-all-around (GAA) FET with ferroelectric in this paper. For the gate structure, a multilayer structure of metal-ferroelectric-metal-insulator-semiconductor (MFMIS) was used, and the SS was calculated in and , which are the ranges of remanent polarization and coercive field suggested in various experiments in the case of HZO as the ferroelectric material. It was found that the SSs from the presented analytical SS model agree well with those derived from the relationship between drain current and gate voltage using a 2D potential distribution in the range of device parameters used for simulation. As a result of analyzing the SS of the junctionless GAA FET with ferroelectric using the analytical SS model presented in this paper, the SS decreased because the voltage across the inner gate decreased when the ferroelectric thickness increased. It was observed that the condition of SS < 60 mV/dec was sufficiently obtained according to changes in device parameters such as channel length, channel radius and ferroelectric thickness, and that the SS maintained a constant value according to the ratio of remanent polarization and coercive field P r / E c . As P r / E c increases, the SS increases as the ferroelectric capacitance increases. As the channel length becomes smaller, the change in SS according to P r / E c is more severe. [ABSTRACT FROM AUTHOR]

Lowering power consumption has emerged as the primary goal as silicon circuits become more compact. Furthermore, the ultra-highly integrated circuit will unavoidably generate a substantial amount of heat. A novel mathematical modeling method is defined for the analysis of a ferroelectric-based negative capacitance field-effect transistor (NCFET) that will adequately address the non-uniformity in polarization switching and subthreshold behavior. This study analyses the I–V and C–V properties of a lithium niobate (LiNbO 3 ) ferroelectric material-based metal–ferroelectric–metal–insulator–semiconductor NCFET. Device parameters including drain current, polarization factor, capacitance, total charge density, and subthreshold swing are evaluated in accordance with the calibration performed considering different variables, such as ferroelectric materials, gate bias modification, and ferroelectric thickness. Numerical simulation is also performed using the Silvaco ATLAS TCAD tool to simulate and calibrate the above-mentioned parameters. MATLAB simulation is initially performed to solve the ferroelectric 1-D Landau–Khalatnikov equation, which is then used for subsequent analyses. The proposed device also starts to exhibit hysteresis behavior at low ferroelectric thicknesses. The simulations demonstrate a 45% increase in the potential curve, thus proving the device to be a viable contender for low-power applications. [ABSTRACT FROM AUTHOR]

Adsorption of gas molecules on the surface of two-dimensional (2D) molybdenum disulfide (MoS2) can significantly affect its carrier transport properties. In this letter, we investigated the effect of a vacuum environment on the electrical properties of a back-gate MoS2 FET. Benefiting from the reduced scattering centers caused by the adsorbed oxygen and water molecules in a vacuum, the current Ion/Ioff ratio of back-gate MoS2 field effect transistor increased from 1.4 × 106 to 1.8 × 107. In addition, the values of field effect carrier mobility were increased by more than four times, from 1 cm2/Vs to 4.2 cm2/Vs. Furthermore, the values of subthreshold swing could be decreased by 30% compared with the sample in ambient air. We demonstrate that the vacuum process can effectively remove absorbates and improve device performances. [ABSTRACT FROM AUTHOR]