Performance optimization of high-K pocket hetero-dielectric TFET using improved geometry design.

This study explores the optimization of a hetero-dielectric tunnel field-effect transistor (HDTFET) structure to improve device performance. By incorporating a high-k oxide pocket in a portion of the source-side gate insulator, a local minimum in the conduction band edge is induced at the source-channel interface. This technique leads to improved tunneling rates and increased current handling capability. The simulation analysis focuses on optimizing the position and dimension of the high-k dielectric pocket to enhance key device characterization metrics such as ON-state current (I ON), ON-to-OFF-state current ratio (I ON / I OFF), subthreshold swing (SS), and cutoff frequency (f T). The resulting optimized design for a 30 nm-channel length involves a pocket shift of 1 nm and a pocket length of 12 nm. This configuration achieves a remarkable ON current of 55 µA/µm, which is 30 times higher than that of a conventional TFET. Importantly, other analog performance parameters remain unaffected, with f T surpassing 175 GHz for the 30 nm-channel. Additionally, transient analysis is conducted by applying a resistive load inverter circuit to a pulse input. The fall propagation delay (t phl) exhibits a greater than two orders of magnitude enhancement, along with improved overshoot voltage (V P) compared to a TFET without a pocket. The study further explores the impact of supply scaling on transient parameters. Optimal pocket scalability concerning channel length is found to be 40% for pocket length and approximately 2.5% for pocket shift relative to the source-channel interface. The proposed design significantly enhances DC and analog as well as circuit-level metrics compared to the traditional uniform gate oxide TFET. [ABSTRACT FROM AUTHOR]