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Smart devices design consists of multiple highly connected electronic device design stages (firmware, PCB layout, application logic, etc.). However, the design tools are separate, specializing in only one design stage, leading to complex design workflows with slow and time-consuming iteration processes. In this dissertation, we explore circuit data information encapsulation techniques for fusing multiple electronic device design steps, creating fast design workflows. We detail these techniques through three design tools: a framework for rapidly generating firmware from web-based applications, an interactive tool for rapidly transforming web pages into functional smart devices, an interactive tool for quickly merging electronic schematics with real-time detection of common errors. This work also presents design automation techniques that are possible with the encapsulation of circuit data information. Small user studies show how these tools can provide an alternative to traditional design workflows by lowering the barrier to entry for beginners and streamlining design for experts.

The “Quantum Dot Cellular Automata” or QCA is mainly used to design and simulate ‘3D’ structures for area-occupation, latency and total power reduction of any electronic circuit. At present, this “Nano-technology world” requires less-complex, small-size, high-frequency, fault-tolerant, low-power devices to increase the component-density in a single die. QCA designs are the well-known and optimum alternative of CMOS designs due to its above mentioned advantages. Further, reversible gates can also be formed based on QCA design. Reversible logic not only reduce the complexity of the design but also it can increase the information storage possibility by saving the power and energy. It is capable of reducing the leakage power (‘KTln2’ amount of dissipated energy for every bit can be ignored due to this logic). Cost of any device depends on the delay, power and occupied-area of the device which can be decreased by reversible multilayer (‘3D’) QCA structures. So, this proposed technique has an ability to provide the design for a cost-effective electronic device with good scalability and fault-tolerance. In the present work, we have simulated of an “Arithmetic and Logic Unit” in “QCA Designer” and “Xilinx” software. The first software is used due to the above advantages and here we apply reversible logic (reversible TSG gate with reversible AND-OR gate). This ALU is capable of performing one arithmetic (addition of two inputs) and three logical operations (AND, OR and XOR operations of two inputs) at a time. The TSG gate is used here as a full-adder with two input XOR operation and The reversible AND-OR gate is utilized for getting the AND result and OR result of two inputs. This design is also required a “4:1 MUX” which helps to select the operations properly. Schematic designs of proposed design with calculated values of delay and total power (for different room-temperature) are achieved in our work by using ‘Xilinx’ simulator. The used Verilog coding of our formed-design is also implemented in a “FPGA Board” (“Spartan 3E”) for hardware verification. Our presented circuitry can also continue its functionalities at high-temperature.

A Local Constrained Multi-Objective Bayesian Optimization (LoCoMOBO) method is introduced to address automatic sizing and trade-off exploration for analog and RF integrated circuits (IC). LoCoMOBO applies to constrained optimization problems utilizing multiple Gaussian Process (GP) models that approximate the objective and constraint functions locally in the search space. It searches for potential pareto optimal solutions within trust regions of the search space using only a few time-consuming simulations. The trust regions are adaptively updated during the optimization process based on feasibility and Hypervolume metrics. In contrast to mainstream Bayesian Optimization approaches, LoCoMOBO uses a new acquisition function that can provide multiple query points, therefore allowing for parallel execution of costly simulations. GP inference is also enhanced by using GPU acceleration in order to handle highly constrained problems that require large sample budgets. Combined with a framework for schematic parametrization and simulator calls, LoCoMOBO provides improved performance trade-offs and sizing results on three real-world circuit examples, while reducing the total run-time up to ×43 times compared to state-of-the-art methods.

In this paper, a novel on-chip dual-band bandpass filter (D-BPF) with two independently controllable transmission zeros (TZs) is proposed. Based on resonators transformation, the schematic and design procedure of the filter are presented. Using even-/odd-mode analysis, analytical equations are used for demonstration of the theory. As an example, a 3.32/5.17-GHz D-BPF with 3-dB fractional bandwidth (3-dB FBW) of 25.45%/14.20% for 5G applications is designed, fabricated, and measured. The size of the filter in low-temperature cofired ceramic (LTCC) is only 11.4 mm * 6 mm * 0.94 mm. The filter has been successfully measured with the minimum insertion loss of 1.38/1.53-dB and high return loss of 28/23-dB at the center frequency.

En los artículos Initial and final finance in the monetary circuit and the effective demand theory (2016), y Endogenous money and the theory of long period effective demand (2020), este último escrito con Stefano di Buccianico, el economista Sergio Cesaratto propone un marco interpretativo para integrar algunos de los elementos de la teoría de la demanda agregada y la teoría monetaria heterodoxa en un solo cuerpo teórico coherente. El objetivo de este texto es presentar de la forma más clara y esquemática posible la propuesta teórica de Sergio Cesaratto, teniendo en cuenta la escaza difusión de las teorías pos-keynesianas en español, y la importancia teórica y analítica para la comprensión del funcionamiento del actual sistema económico capitalista.

To deal with the ever increasing wireless traffic, we have recently designed a vehicular cognitive capability harvesting network (V-CCHN) architecture to leverage vehicles as an alternative “transmission medium” (i.e., an opportunistic data carrier), besides the wireless spectrum, to effectively transport data from the location where it is collected to the place where it is consumed or utilized in a smart city environment. In the V-CCHN, cognitive radio technologies are utilized so that a large amount of data can be exchanged between vehicles and roadside infrastructure during their contacts through short-range high-speed transmissions. Considering the limited contact duration and the uncertain activities of primary users, how to facilitate efficient data exchange between vehicles and roadside infrastructure is very challenging. This problem is further complicated by the fact that the mobility of vehicles might not be accurately predicted. In this paper, we propose a probabilistic data prefetching (PDP) scheme for the V-CCHN to address these challenges so that the contact durations can be efficiently utilized for data exchange. By considering the conditional value at risk, we formulate the PDP schematic design as an optimization problem which allows us to obtain the corresponding PDP scheme. Finally, we have conducted extensive study to evaluate the performance of the obtained PDP scheme under various parameter settings.

The objective of this research heuristic model is to give a outlook on how to carry out a research, from start to finish. This is not just a flow chart; it is a comprehensive research-tackling-guide-model that directs the researcher where to go, what next to do or achieve at any point on the schematic research diagram. Most researchers get confused on what to do, even at the point of discovering the knowledge and research gap. This work paves the way on how the researcher should begin the research work from the start point to the finish point. &nbsp

The presence of Pole-Zero (P-Z) pairs in the open-loop frequency response of CMOS OTAs has always been considered detrimental to the closed-loop operation of OTAs. In this work, a new proposed theory is presented showing how to reduce the impact of such P-Z pairs on the settling time of CMOS OTAs - using low-frequency zeros and cascaded-gain stages - consequently revealing un-tapped opportunities for many-stage CMOS OTA design. The proposed theory will be validated and verified through a design example that also demonstrates how the generalized theory unveils opportunities for many-stage OTA design. The presented example is a 2- to 8-stage CMOS OTA based on the TSMC 65 nm CMOS process, verified through simulations (schematic and post-layout) as well as some measurement results.

Schematic drawings showing railway tracks and equipment are commonly used to visualize railway operations and to communicate system specifications and construction blueprints. Recent advances in on-line collaboration and modeling tools have raised the expectations for quickly making changes to models, resulting in frequent changes to layouts, text, and/or symbols in schematic drawings. Automating the creation of high-quality schematic views from geographical and topological models can help engineers produce and update drawings efficiently. This paper introduces four methods for automatically producing schematic railway drawings with increasing level of quality and control over the result. The final method, implemented in the open-source tool that we have developed, can use any combination of the following optimization criteria, which can have different priorities in different use cases: width and height of the drawing, the diagonal line lengths, and the number of bends. We show how to encode schematic railway drawings as an optimization problem over Boolean and numerical domains, using combinations of unary number encoding, lazy difference constraints, and numerical optimization into an incremental SAT formulation. We compare drawings resulting from each of the four methods, applied to models of real-world engineering projects and existing railway infrastructure. We also show how to add symbols and labels to the track plan, which is important for the usefulness of the final outputs. Since the proposed tool is customizable and efficiently produces high-quality drawings from railML 2.x models, it can be used (as it is or extended) both as an integrated module in an industrial design tool like RailCOMPLETE, or by researchers for visualization purposes.

Handwritten circuit diagrams from educational scenarios or historic sources usually exist on analogue media. For deriving their functional principles or flaws automatically, they need to be digitized, extracting their electrical graph. Recently, the base technologies for automated pipelines facilitating this process shifted from computer vision to machine learning. This paper describes an approach for extracting both the electrical components (including their terminals and describing texts) as well their interconnections (including junctions and wire hops) by the means of instance segmentation and keypoint extraction. Consequently, the resulting graph extraction process consists of a simple two-step process of model inference and trivial geometric keypoint matching. The dataset itself, its preparation, model training and post-processing are described and publicly available., Comment: As submitted to ICPRAM23

To broaden the absorbing frequency band of radar-absorbing material (RAM), a simple radar-absorbing structure (RAS) with square pore was designed and prepared by 3D printing and coating dipping methods to verify the reliability of the design in this paper. On this basis, the gradient optimization design of sheet resistance of the structure was carried out to investigate the effect of gradient sheet resistance on the radar-absorbing performance. The results show that the sheet resistance and wall thickness of the structure have significant influence on the reflection loss peak and the absorbing bandwidth. When the side length L = 15 mm, the sheet resistance R = 500 Ω/sq, the height H = 20 mm, and the wall thickness w = 1.0 mm, the effective radar-absorbing bandwidth with a reflection loss below −10 dB can reach 15.82 GHz in the frequency band of 1–18 GHz. After the gradient optimization design of sheet resistance, the radar-absorbing bandwidth is wider and the absorbing curve is flatter, the gradient design of sheet resistance with appropriate tolerance can further improve the radar-absorbing performance of broadband. This RAS provided a new technical way for the development of “thin, light, wide, and strong” RAMs. (1) The schematic diagram and equivalent circuit model of square-hole structure; (2) The simulation and test results of the square-hole structure

The operation process of free-piston engine generator (FPEG) can be divided into starting process and power generation process, and each of them faces severe challenges especially for the opposed-piston FPEG. As the first part of the investigation, this paper focuses the starting process of opposed piston FPEG. Two novel general methods to start the opposed-piston FPEG are investigated by the linear electric machine operating as linear motor. Both simulation and test results are presented, and the numerical model is successfully validated. The test results show that the maximum in-cylinder pressure of the engine cylinder is 11.85bar, indicating that the engine is ready for ignition, and the synchronization error of opposed-piston fluctuates within ± 2 mm with the limitation of the synchronization mechanism Further investigations on the opposed-piston scheme performance with the displacement master–slave control strategy and current master–slave control strategy are carried out. The results demonstrate that both control strategies are feasible to start the opposed-piston FPEG. More importantly, the current master–slave control strategy has faster response to external interference and therefore the piston synchronization error is smaller. And the smaller motor force of the current master–slave control strategy makes the peak in-cylinder pressure reach the target value. Further research shows that the mass of moving parts, constant motor force and the synchronization mechanism are crucial factors for such schematic prototype during starting process.

We advocate the use of de Bruijn's universal abstraction $\lambda^\infty$ for the quantification of schematic variables in the predicative setting and we present a typed $\lambda$-calculus featuring the quantifier $\lambda^\infty$ accompanied by other practically useful constructions like explicit substitutions and expected type annotations. The calculus stands just on two notions, i.e., bound rt-reduction and parametric validity, and has the expressive power of $\lambda\rightarrow$. Thus, while not aiming at being a logical framework by itself, it does enjoy many desired invariants of logical frameworks including confluence of reduction, strong normalization, preservation of type by reduction, decidability, correctness of types and uniqueness of types up to conversion. This calculus belongs to the $\lambda\delta$ family of formal systems, which borrow some features from the pure type systems and some from the languages of the Automath tradition, but stand outside both families. In particular, the calculus includes and evolves two earlier systems of this family. Moreover, a machine-checked specification of its theory is available., Comment: 37 pages, minor revision

This paper analyzes the double staircase from a topological point of view in three parts. First, it surveys historical archetypes of the double staircase, attending to their evolution and sundry topological varieties. Second, it presents a topological taxonomy for the double staircase which allows its rigorous formal classification. Third, it explores the generative range of algorithmically generated double staircases, particularly those derived directly from schematic circulation schemes. We introduce the medial axis as a technique uniquely suited to produce rich spatial models of double staircases from abstract topological diagrams. Through this investigation, we furnish a framework for the analysis and generation of models of the double staircase that embody various topological and spatial qualities. By interweaving historical taxonomies with contemporary practices of computational design, this study reintroduces the double staircase as an enduringly vital mode of architectural investigation.

In the modern evolution, WSN (Wireless Sensor Network) incorporated with data aggregation platform which involves stimulating research area with various modern upgradation of AI (Artificial Intelligence). Many types of research are carried out by undertaking variety of Deep Learning Network and Fuzzy based data aggregation techniques in the interpretation of Wireless Sensor Circumstance. The focal theme of the proposed research paper is to analyze the present concentrated work on Artificial Intelligence-accompanied data aggregation paradigm in wireless communication by elaborating the integration framework. By this proposed AI with data aggregation wireless sensor system has upgraded the innovation with high empowering pillars in analyzing the data with more processing and interpretations. Since it also improves the data transmission rate by providing more security and encryption schemes to the preprocessed data storing and streaming ton the bandwidth channels. This paper enumerates the AI contribution on the computing platform with the various advancement of blockchain technology schematic framework and further its case study experimentation on the aero-engine applications. Further experimental results are provided with numerical analysis by showing the traditional and advanced- Long term Memory technique prediction results by taking aero-engine wireless sensor network environment through MATLAB simulation.

This study reports on two knowledge elements of stance and schematic structure in order to help novice students increase the efficacy of their writing in business communication. With this regard, Santos’ (2002) Business Letters of Negotiation Model and Hyland’s (2005b) Stance Model of Interaction were drawn upon. Sixty business emails written by native English speaking (NS) and Iranian students of Business Management Departments in universities were analyzed. Two raters explored the corpus for their moves/steps frequencies and a concordance software was used in order to explore stance markers frequencies. To investigate whether Iranian and NS writers are statistically different from each other, the findings of frequencies were submitted to one-variable Chi-square test. The results showed that NS and Iranian writers are not different from each other in their content staging while they are providing information/answers or negotiating. Running counter to moves 2 and 23, move 3 turned out to have different results; there was a significant difference between NS and Iranian writers in their request of information/action/favors. Results presented no significant difference between NS and Iranian writers in their employment of hedges and attitude markers of stance with regard to one-variable Chi-square test results. For boosters, Chi-square test detected a significant difference between the groups only in move 2. There was a significant difference, however, between NS and Iranian writers in their use of self-mention markers in moves 3 and 23. The results of this paper have both theoretical and pedagogical significance.

The identification of new applications for sketching and freehand drawing in the field of engineering is a subject of interest for researchers and practitioners, especially after a significant drop...

Single-flux-quantum (SFQ) circuits operate at higher frequencies with much lower power consumption when compared to their CMOS counterparts. Synchronous SFQ circuits require full path balancing by inserting D-Flipflops as needed, an operation that tends to greatly increase the number of gates in a circuit. To control this increase in the total number of gates, complex multi-input SFQ logic gates can be built and used to synthesize the circuits. In this work, a 1-b full adder is built with sum and carries as two individual single-stage SFQ gates. Both of the sum and the carry cells are demonstrated with their schematics and layouts. Postlayout simulation based on the extracted circuit parameters by InductEx is done by using JSIM and demonstrates the correct functionality of the proposed full adder design. Later, an 8-b signed multiplier using this newly designed single-stage full adder is implemented to illustrate the advantages of the new design. The structure and timing strategy of the multiplier as well as the simulation result are shown. In the end, circuits of different sizes are synthesized with the single-stage full adder circuit, and the results are discussed.