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β-Ga2O3 thin films with both a 45 nm Si-doped conductive epilayer and unintentionally doped epilayer were grown on c-plane sapphire substrate by metalorganic chemical vapor deposition. β-Ga2O3 based metal–oxide–semiconductor field-effect transistors (MOSFETs) were fabricated with gate recess depths of 20 nm and 40 nm (it indicated gate depth with 70 nm and 50 nm, respective), respectively, and without said recessing process. The conductivity of β-Ga2O3 epilayers was improved through low in situ doping using a tetraethoxysilane precursor to increase MOSFET forward current density. After recessing, MOSFET operation was transferred from depletion to enhanced mode. In this study, the maximum breakdown voltage of the recessed 40 nm transistor was 770 V. The etching depth of a recessed-gate device demonstrates its influence on device electrical performance. [ABSTRACT FROM AUTHOR]

This paper reports on TCAD simulation of beta-gallium oxide (β-Ga2O3) MOSFET with the channel recessed into a 1-µm thick Si-doped (1 × 1018 cm−3) epitaxial layer. We optimized gate recess thickness to achieve both depletion mode (D-mode) and enhancement mode (E-mode) operations. The simulated β-Ga2O3 MOSFET structures show optimum D-mode and E-mode characteristics for 150-nm and 15-nm active channel thicknesses, respectively. A comparative study is also done to analyze the thermal and electrical effects by simulating the heteroepitaxial β-Ga2O3 layer on sapphire substrate [201] and homoepitaxial β-Ga2O3 layer on β-Ga2O3 [010] substrate. The MOSFET devices based on the β-Ga2O3 layers on sapphire substrates show improved performance compared to the devices based on the β-Ga2O3 layers on β-Ga2O3 substrates in terms of drain current, transconductance, and breakdown voltage. β-Ga2O3 epitaxial layers on sapphire substrates exhibit a drain current density of 425 mA/mm with a peak transconductance of 12.2 mS/mm for D-mode operation and 153 mA/mm drain current density with a peak transconductance of 20.8 mS/mm for E-mode operation. In contrast, the MOSFET devices based on the β-Ga2O3 epitaxial layers on β-Ga2O3 substrates show a drain current density of 415 mA/mm for D-mode operation and 144 mA/mm drain current density with 3.2 mS/mm peak transconductance for E-mode operation. The MOSFET devices based on the β-Ga2O3 epitaxial structures on sapphire and β-Ga2O3 substrates show reliable switching properties with improved subthreshold slope and high Ion/Ioff ratio of 1011. These simulation results show potential of laterally scaled β-Ga2O3 MOSFETs for power-switching applications. [ABSTRACT FROM AUTHOR]

In this paper, a novel recessed T-gate double channel HEMT with InGaN back barrier has been designed and studied. The double channel is formed by the AlN layer's insertion below the InAlN/GaN interface, enhancing the drain current density (2.5A/mm). However, double channel HEMT suffers from a lack of gate controllability, due to which device performance decreases. This problem has been resolved by using the InGaN as a back barrier which enhances the carrier confinement of 2DEG by raising the conduction band for the GaN buffer and significantly enhances the gate controllability over a lower channel. Precisely a brief comparison has been done of the proposed device with conventional double channel HEMT. Performance parameters like drain current (Ids), transconductance (gm), intrinsic gain (Av), output conductance (gd), early voltage (VEA), TGF, parasitic capacitances (Cgs, Cgd), cut-off frequency (fT), maximum oscillation frequency (fmax), gain frequency product (GFP), transconductance frequency product (TFP), and gain transconductance frequency product (GTFP) have been investigated. Further, the improvement in linearity parameters such as VIP2, VIP3, IIP3, and 1-dB compression point has been observed by varying the back barrier distance from the lower channel. [ABSTRACT FROM AUTHOR]

A physics-based analytical model for GaN high-electron-mobility transistors (HEMTs) with non-recessed- and recessed-gate structure is presented. Based on this model, the two-dimensional electron gas density (2DEG) and thereby the on-state resistance and breakdown voltage can be controlled by varying the barrier layer thickness and Al mole fraction in non-recessed depletion-mode GaN HEMTs. The analytical model indicates that the 2DEG charge density in the channel increases from 2.4 × 1012 cm−2 to 1.8 × 1013 cm−2 when increasing the Al mole fraction from x = 0.1 to 0.4 for an experimental non-recessed-gate GaN HEMT. In the recessed-gate GaN HEMT, in addition to these parameters, the recess height can also control the 2DEG to achieve high-performance power electronic devices. The model also calculates the critical recess height for which a normally-ON GaN switch becomes normally-OFF. This model shows good agreement with reported experimental results and promises to become a useful tool for advanced design of GaN HEMTS. [ABSTRACT FROM AUTHOR]

Abstract In this paper, a silicon-based T-shape gate dual-source tunnel field-effect transistor (TGTFET) is proposed and investigated by TCAD simulation. As a contrastive study, the structure, characteristic, and analog/RF performance of TGTFET, LTFET, and UTFET are discussed. The gate overlap introduced by T-shape gate can enhance the efficiency of tunneling junction. The dual-source regions in TGTFET can increase the on-state current (I ON) by offering a doubled tunneling junction area. In order to further improve the device performance, the n+ pocket is introduced in TGTFET to further increase the band-to-band tunneling rate. Simulation results reveal that the TGTFET’s I ON and switching ratio (I ON/I OFF) reach 81 μA/μm and 6.7 × 1010 at 1 V gate to source voltage (V g). The average subthreshold swing of TGTFET (SSavg, from 0 to 0.5 V V g) reaches 51.5 mV/dec, and the minimum subthreshold swing of TGTFET (SSmin, at 0.1 V V g) reaches 24.4 mV/dec. Moreover, it is found that TGTFET have strong robustness on drain-induced barrier lowering (DIBL) effect. The effects of doping concentration, geometric dimension, and applied voltage on device performance are investigated in order to create the TGTFET design guideline. Furthermore, the transconductance (g m), output conductance (g ds), gate to source capacitance (C gs), gate to drain capacitance (C gd), cut-off frequency (f T), and gain bandwidth (GBW) of TGTFET reach 232 μS/μm, 214 μS/μm, 0.7 fF/μm, 3.7 fF/μm, 11.9 GHz, and 2.3 GHz at 0.5 V drain to source voltage (V d), respectively. Benefiting from the structural advantage, TGTFET obtains better DC/AC characteristics compared to UTFET and LTFET. In conclusion, the considerable good performance makes TGTFET turn into a very attractive choice for the next generation of low-power and analog/RF applications.

Junctionless Metal Oxide Semiconductor Field-Effect Transistor (JL MOSFET) is one of the promising candidate to replace the junction based MOSFET for upcoming technology nodes. Semiconductor industries are continuously urging for large ON current with the low OFF current and low specific on resistance. However, high ON current is achieved in Conventional (Conv.) JL DG MOSFET by using high doping concentration at the cost of high OFF current which leads depletion mode operation. Moreover, low doping, narrow channel thickness and high work function gate materials are using to operate Conv. JL DG MOSFET in enhancement mode (Vth > 0 V for N-JL DG MOSFET, Vth < 0 V for P-JL DG MOSFET) but ON current is reduced in all above mentioned solutions. To overcome the above mentioned problems, a new architecture is developed called Recessed JL DG MOSFET. In Recessed JL DG MOSFET silicon region is recessed under the gate region and some gate portion is extended towards source and drain region. Recessed JL DG MOSFET shows the same ON current as achieved in Conv. JL DG MOSFET with very low OFF current (leakage current) by considering high doping concentration. Surface potential, electron density, energy band distribution, drain current have been investigated to proof the enhancement mode operation of Recessed JL DG MOSFET. Figure of Merits (FOMs) for RF performance such as Trans-conductance, capacitance and intrinsic power gain (S21), Trans-conductance frequency product (TFP), Gain frequency product (GFP) and Gain trans-conductance frequency product (GTFP) have also investigated of Recessed JL DG MOSFET. [ABSTRACT FROM AUTHOR]

An enhancement-mode AlGaN/GaN metal-insulator-semiconductor high-electron- mobility-transistor was fabricated using a recess gate and CF4 plasma treatment to investigate its reliable applicability to high-power devices and circuits. The fluorinated-gate device showed hysteresis during the DC current-voltage measurement, and the polarity and magnitude of hysteresis depend on the drain voltage. The hysteresis phenomenon is due to the electron trapping at the Al2O3/AlGaN interface and charging times longer than milliseconds were obtained by pulse I-V measurement. In addition, the subthreshold slope of the fluorinated-gate device was increased after the positive gate bias stress because of the two-dimensional electron gas reduction by ionized fluorine. Our systematic observation revealed that the effect of fluorine ions should be considered for the design of AlGaN/GaN power circuits.

In this work, recessed gate AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) with double AlGaN barrier designs are fabricated and investigated. Two different recessed depths are designed, leading to a 5 nm and a 3 nm remaining bottom AlGaN barrier under the gate region, and two different Al% (15% and 20%) in the bottom AlGaN barriers are designed. First of all, a double hump trans-conductance (gm)−gate voltage (VG) characteristic is observed in a recessed gate AlGaN/GaN MIS-HEMT with a 5 nm remaining bottom Al0.2Ga0.8N barrier under the gate region. Secondly, a physical model is proposed to explain this double channel characteristic by means of a formation of a top channel below the gate dielectric under a positive VG. Finally, the impacts of Al% content (15% and 20%) in the bottom AlGaN barrier and 5 nm/3 nm remaining bottom AlGaN barriers under the gate region are studied in detail, indicating that lowering Al% content in the bottom can increase the threshold voltage (VTH) toward an enhancement-mode characteristic.

Enhancement-mode transistors with uniform turn-on threshold voltage (V th ) can be achieved using low damage and low rate gate recess etching techniques. In this work, dry etching conditions for a AlGaN/GaN heterostructure with an ultra-low etching rate of 1.5 nm/min were demonstrated and we succeeded the possibility to achieve a low etch rate of an AlGaN/GaN heterostructure in a Cl 2 /BCl 3 plasma using inductively coupled plasma (ICP). The etching development was successfully implemented in the achievement of a normally-off GaN/AlGaN based transistor. The optimal recess depth was determined after fabrication of various devices with different recess depth values and with various dry etching conditions and after examining the performances of fabricated devices various conditions, and determining the dependence of recess time. The optimized etching condition resulted in low damage and smooth morphology of the etched AlGaN/GaN surfaces. Fine control of the depth of the gate region recess was achieved for the AlGaN/GaN heterostructure without any etch-stop layer, and validated for the fabrication of field effect transistors (FETs) using conventional processes. The fabricated normally-off Al 2 O 3 /AlGaN/GaN MOSFETs delivered a high positive V th of +5.64 V with a low off-state leakage current of ∼10 −7  A/mm and lower current collapse. [ABSTRACT FROM AUTHOR]

The subthreshold characteristic of gate-recessed high-electron-mobility transistors (HEMTs) using dual-gate (DG) architectures is systematically studied. The recessed DG structure can effectively shift the threshold voltage ( V\text {th} ) in the positive direction. Different from the complex function expression between V\text {th} and AlGaN thickness ( \texttb ) in the recessed single-gate (SG) device, the variation of \textV\text {th} with tb is monotonic in the recessed DG devices. Recessed DG device exhibits a low off-state leakage current of \sim 3\times 10^-10 A/mm and gate induced drain leakage is effectively improved. A higher I \mathrm{\scriptscriptstyle ON}/I \mathrm{\scriptscriptstyle OFF} range of recessed DG devices broadens about 2 times and provide a wider range of tb than that of recessed SG devices. The DG structure has a stronger modulation effect on drain–source resistance ( R\text {ds} ) and gate–drain resistance ( R\text {gd} ) than the SG devices. A lower subthreshold swing (SS) of ~100 mV/dec is obtained by recessed DG design. Due to the second gate inducing the lateral extension of depletion region between the first gate and drain, the off-state leakage and first gate reverse leakage have been significantly improved. Therefore, the recessed DG architecture design can effectively improve the fluctuation of SS and off-state current versus the different AlGaN barrier thickness. [ABSTRACT FROM PUBLISHER]

The DC and microwave characteristics of 20 nm gate length (L g ) InAlN/GaN High electron mobility transistor (HEMT) on SiC substrate with heavily doped source and drain region have investigated for both depletion mode (D-mode) and Enhancement mode (E-mode) operation using Synopsys TCAD tool. The simulation is performed at room temperature by using drift-diffusion model. The device having the features of recessed T - gate structure, InGaN back barrier and Al 2 O 3 passivated device surface. The proposed novel Lg = 20 nm, W = 2 × 40 μm D-mode (E-mode) HEMT exhibited a peak drain current density (I dmax ) of 2.7 (2.6) A/mm, transconductance (g m ) of 1.04 (1.63) S/mm, current gain cut-off frequency (f t ) of 310 (343) GHz and power gain cut-off frequency (f max ) of 364 (236) GHz. The measured carrier mobility (μ), sheet charge carrier density (n s ) and breakdown voltage are 1580 (1615) cm 2 /V−s, 1.9 × 10 13 (1.93) Cm −2 and 10.7 (12.8) V respectively. The superlatives of the proposed HEMTs are bewitching competitor for future sub-millimetre wave high power RF VLSI circuit applications. [ABSTRACT FROM AUTHOR]

The DC and RF performance of 30nm gate length enhancement mode (E-mode) AlGaN/AlN/GaN High electron mobility transistor (HEMT) on SiC substrate with heavily doped source and drain region have investigated using Synopsys TCAD tool drift diffusion model at room temperature. The proposed device features are recessed T - gate structure, InGaN back barrier and Si3N4 passivated device surface. The HEMT exhibits a maximum drain current density of 2.1 [A/mm], transconductance gm of 1680 [mS/mm], current gain cut-off frequency frequency ft of 220 GHz and power gain cut-off frequency fmax of 245 GHz. At room temperature the measured carrier mobility (μ), sheet charge carrier density (ns) and breakdown voltage are 1400 (cm2/V - s ), 1.6 X1013 (Cm-2) and 14 V respectively. The excellent DC and microwave performance of the proposed HEMT is promising candidate for future high power RF applications. [ABSTRACT FROM AUTHOR]

This experimental study focuses on the positive bias temperature instability (PBTI) in a fully recessed-gate AlGaN/GaN MOS-HEMT. A positive stress voltage to the gate results in positive threshold voltage shift (ΔV th ), which is attributed to the trapping of electrons from the GaN layer into the pre-existing oxide traps. The trapping rate exhibits a universal decreasing behavior as a function of the number of filled traps, independently of stress time, stress voltage, stress temperature, and device-to-device variability. The stress-induced ΔV th can be fully recovered by applying a small negative voltage, which causes the electron de-trapping. In the explored time window (between 1 s and thousands of s), the recovery dynamics is well described by the superimposition of two exponential functions associated with two different traps. Both trap time constants are independent of the stress voltage, decrease with temperature and increase with the recovery voltage. The activation energy of the slower trap is 0.93 eV, while the faster trap exhibits an activation energy with a large spread in the range between 0.45 eV and 0.82 eV. [ABSTRACT FROM AUTHOR]

In this paper, a normally off Al2O3/AlN/GaN MISFET on Si substrate for achieving high threshold voltage stability and uniformity is obtained based on selective area growth. A thin AlN space layer (SL, ~1 nm) is adopted to GaN-based template, and the AlGaN/GaN het-erostructureis selectivelygrownon the template to naturally form a recessed structure. By insertion of the AlN SL, the Al2O3/AlN/GaN interface trapping and scattering effects are effectively suppressed. As a result, a low threshold voltage hysteresis ( \Delta V\mathrm{ th} , 80 mV at maximum gate sweep voltage of 10 V by dc I – V measurement and smaller than 200 mV in linear region by pulse I – V measurement) and a high peak field-effect mobility ( \mu \sf FE) of 192 cm2/ \textV\cdot \texts are obtained in Al2O3/AlN/GaN MISFET. It is a significant improvement compared with Al2O3/GaN MISFET without AlN SL. The Al2O3/AlN/GaN MISFET also exhibits a maximum drain current ( Id,max) of 620 mA/mm, a low on-resistance ( Rds, \mathrm\scriptscriptstyle ON) of $9.6~\Omega \cdot $ mm, and a high uniformity of {V}_{\mathrm{ th}} (2.5 ± 0.1 V). [ABSTRACT FROM PUBLISHER]

In this paper, fully recessed-gate GaN MISFETs with two different gate dielectrics, i.e., plasma-enhanced atomic layer deposition (PEALD) SiN and ALD Al2O3 gate dielectric, are used to study the origin of positive bias temperature instability (PBTI). By employing a set of dedicated stress-recovery tests, we study PBTI during the stress and relaxation. Hence, a defect band model with different distributions of defect levels inside the gate dielectric is proposed, which can excellently reproduce the experimental data and provide insightful information about the origin of PBTI in GaN MISFETs. The results indicate that the serious PBTI in the device with PEALD SiN is mainly due to a wide distribution of defect levels ( \sigma \sim 0.67 eV), centered below the conduction band of GaN ( E_{C} -0.05 eV), and can be easily accessed by the channel carriers already at a low-gate voltage. On the other hand, ALD Al2O3 gate dielectric shows a narrower distribution of defects ( \sigma \sim 0.42$ eV), which are far from the conduction band of GaN ( E_{C} +1.15 eV). This observations explain the improved PBTI reliability observed in devices with ALD Al2O3. [ABSTRACT FROM AUTHOR]

A novel SOI MESFET with the modified depletion region using a Triple Recessed Gate (TRG-SOI MESFET) is presented for RF applications. The proposed gate consists of lower and upper gate to control the channel thickness and the depletion layer will change by omitting part of total charge due to locating gate in the channel. The key idea of this shaped gate is to modify the depletion region and the charge distribution of the channel in order to lower the electric field of the device and improving the breakdown voltage. In addition the maximum power density, the maximum oscillation frequency, the cutoff frequency, and the minimum noise figure for the proposed structure are improved due to increasing the drain-source resistance and the transconductance and decreasing the gate resistance. Therefore, the TRG-SOI MESFET can be used for high-power and high frequency applications. [ABSTRACT FROM AUTHOR]

This paper addresses scaling issues in AIGaN/GaN heterojunction field-effect transistor's (HFETs) using ensemble Monte Carlo techniques. For gate lengths below 0.25 μm, ƒT values are known not to scale linearly with the inverse gate length. The authors' simulations show this to be due to an increasing difference between the lithographic gate length and the effective gate length as the devices shrink. The results for AIGaN/GaN are compared with In0.52Al0.48-In0.53Ga0.47As-InP devices, and the authors found that the limiting role of velocity overshoot and depletion region spread causes the GaN HFETs to have a peak ƒT of ∼ 220 GHz compared to ∼ 500 GHz for InGaAs devices. [ABSTRACT FROM AUTHOR]

A recessed-gate structure has been studied with a view to realizing normally off operation of high-voltage AlGaN/GaN high-electron mobility transistors (HEMTs) for power electronics applications. The recessed-gate structure is very attractive for realizing normally off high-voltage AlGaN/GaN HEMTs because the gate threshold voltage can be controlled by the etching depth of the recess without significant increase in on-resistance characteristics. With this structure the threshold voltage can be increased with the reduction of two-dimensional electron gas (2DEG) density only under the gate electrode without reduction of 2DEG density in the other channel regions such as the channel between drain and gate. The threshold-voltage increase was experimentally demonstrated. The threshold voltage of fabricated recessed-gate device increased to -0.14 V while the threshold voltage without the recessed-gate structure was about -4 V. The specific on-resistance of the device was maintained as low as 4 mΩ ∙ cm² and the breakdown voltage was 435 V. The on-resistance and the breakdown voltage tradeoff characteristics were the same as those of normally on devices. From the viewpoint of device design, the on-resistance for the normally off device was modeled using the relationship between the AlGaN layer thickness under the gate electrode and the 2DEG density. It is found that the MIS gate structure and the recess etching without the offset region between recess edge and gate electrode will further improve the on-resistance. The simulation results show the possibility of the on-resistance below 1 mΩ ∙ cm² for normally off AlGaN/GaN HEMTs operating at several hundred volts with threshold voltage up to + 1 V. [ABSTRACT FROM AUTHOR]

This article critically reviews the materials, processing and reliability of InP high electron mobility transistors (InP HEMTs) for future terahertz wave applications. The factors such as drain current (I D) over 1200 mA/mm, transconductance (g m) over 3000 mS/mm, cut off frequency (f T) over 700 GHz and maximum oscillation frequency (f max) over 1300 GHz makes InP HEMTs suitable for Terahertz wave applications. Furthermore, low DC power consumption and outstanding low noise performance makes InP HEMT most appropriate transistor technology for the development of space based receivers. This review article critically assesses the challenges in miniaturization of InP HEMTs, doping strategies in InP HEMTs, buried platinum technology, impact of annealing process and temperature, influence of electron and proton irradiation, thermal and bias stress on the reliability of InP HEMTs, cavity and gating effects and influence of trapping effects. InP HEMTs are very much preferable in applications like radio astronomy, terahertz optical and wireless communication systems, atmospheric imaging and sensing, automotive radar, ground based receivers in deep space networks, terahertz imaging and sensing, biomedical applications, security screening, video conferencing & real time multimedia file transfer, high speed and ultra low power digital integrated circuits. [ABSTRACT FROM AUTHOR]

An enhancement-mode AlGaN/GaN metal-insulator-semiconductor high-electron- mobility-transistor was fabricated using a recess gate and CF4 plasma treatment to investigate its reliable applicability to high-power devices and circuits. The fluorinated-gate device showed hysteresis during the DC current-voltage measurement, and the polarity and magnitude of hysteresis depend on the drain voltage. The hysteresis phenomenon is due to the electron trapping at the Al2O3/AlGaN interface and charging times longer than milliseconds were obtained by pulse I-V measurement. In addition, the subthreshold slope of the fluorinated-gate device was increased after the positive gate bias stress because of the two-dimensional electron gas reduction by ionized fluorine. Our systematic observation revealed that the effect of fluorine ions should be considered for the design of AlGaN/GaN power circuits. [ABSTRACT FROM AUTHOR]

We demonstrate a 100-nm-gate-recessed n-GaN/AIGaN/GaN high-electron mobility transistor (HEMT) with low-noise properties at 30 GHz. The recessed GaN HEMT exhibits a low ohmic-contact resistance of 0.28 11 . mm and a low gate leakage current of 0.9 μA/mm when biased at VGS = -3 V and VDS = 10 V. At the same bias point, a minimum noise figure of 1.6 dB at 30 GHz and an associated gain of 5 dB were achieved. To the best of our knowledge, this is the best noise performance reported at 30 GHz for gate-recessed A1GaN/GaN HEMTs. [ABSTRACT FROM AUTHOR]

In this letter, a novel process for recessed-gate AIGaN/GaN high-electron-mobility transistors using an Al2O3/ SiNx, dielectric has been developed. The Al2 03/SiN,1, dielectric bilayer was used as a recess etch-mask for short-gatefootprint definition. Recessed-gate devices with a gate length of 70 nm have been fabricated on a molecular-beam-epitaxygrown layer structure using this process. After the removal of the dielectric layers, excellent dc and small-signal results, a high drain-current density of 1.5 A/mm, a unity gain cutoff frequency of 160 GHz, and a maximum frequency of oscillation of 200 GHz were obtained. [ABSTRACT FROM AUTHOR]

In this work, recessed gate AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) with double AlGaN barrier designs are fabricated and investigated. Two different recessed depths are designed, leading to a 5 nm and a 3 nm remaining bottom AlGaN barrier under the gate region, and two different Al% (15% and 20%) in the bottom AlGaN barriers are designed. First of all, a double hump trans-conductance (gm)–gate voltage (VG) characteristic is observed in a recessed gate AlGaN/GaN MIS-HEMT with a 5 nm remaining bottom Al0.2Ga0.8N barrier under the gate region. Secondly, a physical model is proposed to explain this double channel characteristic by means of a formation of a top channel below the gate dielectric under a positive VG. Finally, the impacts of Al% content (15% and 20%) in the bottom AlGaN barrier and 5 nm/3 nm remaining bottom AlGaN barriers under the gate region are studied in detail, indicating that lowering Al% content in the bottom can increase the threshold voltage (VTH) toward an enhancement-mode characteristic. [ABSTRACT FROM AUTHOR]

In this paper, a silicon-based T-shape gate dual-source tunnel field-effect transistor (TGTFET) is proposed and investigated by TCAD simulation. As a contrastive study, the structure, characteristic, and analog/RF performance of TGTFET, LTFET, and UTFET are discussed. The gate overlap introduced by T-shape gate can enhance the efficiency of tunneling junction. The dual-source regions in TGTFET can increase the on-state current (ION) by offering a doubled tunneling junction area. In order to further improve the device performance, the n+ pocket is introduced in TGTFET to further increase the band-to-band tunneling rate. Simulation results reveal that the TGTFET’s ION and switching ratio (ION/IOFF) reach 81 μA/μm and 6.7 × 1010 at 1 V gate to source voltage (Vg). The average subthreshold swing of TGTFET (SSavg, from 0 to 0.5 V Vg) reaches 51.5 mV/dec, and the minimum subthreshold swing of TGTFET (SSmin, at 0.1 V Vg) reaches 24.4 mV/dec. Moreover, it is found that TGTFET have strong robustness on drain-induced barrier lowering (DIBL) effect. The effects of doping concentration, geometric dimension, and applied voltage on device performance are investigated in order to create the TGTFET design guideline. Furthermore, the transconductance (gm), output conductance (gds), gate to source capacitance (Cgs), gate to drain capacitance (Cgd), cut-off frequency (fT), and gain bandwidth (GBW) of TGTFET reach 232 μS/μm, 214 μS/μm, 0.7 fF/μm, 3.7 fF/μm, 11.9 GHz, and 2.3 GHz at 0.5 V drain to source voltage (Vd), respectively. Benefiting from the structural advantage, TGTFET obtains better DC/AC characteristics compared to UTFET and LTFET. In conclusion, the considerable good performance makes TGTFET turn into a very attractive choice for the next generation of low-power and analog/RF applications. [ABSTRACT FROM AUTHOR]