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Microgrids, featuring distributed generators like solar energy and hybrid energy storage systems, represent a significant step in addressing challenges related to the greenhouse effect and outdated transmission infrastructures. The operation and control of islanded microgrids, particularly in terms of grid voltage and frequency, rely on the synchronization of multiple parallel inverters connected to the distributed generators. However, to determine the necessary grid parameters for effective control, the presence of circulating currents from unbalanced grid voltages arises as a challenge. This situation necessitates the development of a new approach to achieve phase angle locking for grid synchronization, with the aim of maintaining the voltage within acceptable limits in islanded microgrids. This objective is realized through the creation of a microgrid network model, design of an adaptive filter, utilizing the double second-order generalized integrator-phase-locked loop (DSOGI-PLL), for dynamic voltage transformation. The design is evaluated by simulation using MATLAB/Simulink. The primary goal is to investigate the DSOGI-PLL-based droop control and compare its performance with the conventional synchronous reference frame-phaselocked loop (SRF-PLL) control approach. Notably, the DSOGI-PLL successfully eliminates the ripples in phase angle estimation, consequently enhancing the quality of voltage output in the microgrid. [ABSTRACT FROM AUTHOR]

The power grid of a multi-electric aircraft is a typical isolated island microgrid with a wide frequency range from 360 to 800 Hz. The dynamic performance of the traditional constant-frequency power grid synchronization method is insufficient in the variable frequency power grid of the multi-electric aircraft. An adaptive enhanced complex-coefficient filter-based phase locked loop (AECCF-PLL) is designed for the variable frequency power grid by integrating an adaptive module into the enhanced complex-coefficient filter-based phase locked loop to accurately estimate the state of variable frequency power grid. The relationship between the transfer function and the step response is analyzed. The relationship between the model parameters and the frequency is derived, and the frequency adaptive module is established to meet the requirements for stability and rapidity in the state estimation of the variable frequency power grid. The experimental results show that the proposed AECCF-PLL can achieve the rapid and stable estimation of the state of the variable frequency power grid when there are disturbances such as large or small frequency jumps, harmonics and slopes.

Recently, there has been a huge advancement in renewable energy integration in power systems. Power converters with grid-forming or grid-following topologies are typically employed to link these decentralized power sources to the grid. However, because distributed generation has less inertia than synchronous generators, their use of renewable energy sources threatens the electrical grid's reliability. Suitable control approaches for ensuring frequency and voltage stability in the grid-connected form of operation are established in this study, which offers dynamic, seamless power switching in the islanded mode of operation. In this research, effective Phase Locked Loop (PLL) techniques for grid-forming (GFM) and grid-following (GFL) converters are designed to achieve a smooth transition from grid-tied to islanded mode of operation. In this work, PLL configurations are implemented while considering the active and reactive power, frequency, voltage, and current parameters of the system, and ensuring voltage and frequency stability. The simulation results in a microgrid network that ensures a smooth transition of power transfer while switching between modes of operation, and supports the voltage and frequency stability of the system. [ABSTRACT FROM AUTHOR]

Abstract As the boost of power electronics technology, the harmonic problem in the power system is becoming increasingly prominent. Fourier decomposition is performed on the load current in the power system, and components with a frequency that is an integer multiple of the fundamental wave are referred to as harmonic components. Harmonic control is essential to establish a safe and reliable power grid environment and provide high-quality and clean electricity to power users. The study focused on parallel active power filters, proposed a specific harmonic detection method on the grounds of synchronous harmonic rotating coordinate system, and developed a phase-locked loop design on the grounds of order generalized integrator. Meanwhile, a compensation current control method on the grounds of space vector pulse width modulation was introduced. The results showed that in the full compensation simulation experiment, the compensated A-phase grid side current waveform was significantly improved and presented a sinusoidal shape. After 0.05 s, the actual output compensation current closely followed the command current. Meanwhile, after compensation, the total harmonic distortion rate decreased from 26.58 to 3.06%. In specific harmonic compensation simulation experiments, when the sum of 5th, 7th, and 11th harmonic components was used as the command current for compensation, the distortion of the current waveform was improved after the load undergoes a sudden change. After compensation, the 5th, 7th, and 11th harmonic content significantly decreased, and the total harmonic distortion rate decreased to 4.08%. This indicated that the proposed phase-locked loop design and harmonic detection method for active power filters had high stability and effectiveness. The study’s primary contribution is to enhance the utilization efficiency of DC voltage and improve the dynamic response ability of current. Additionally, it offers a new method for reducing the impact of harmonics on the power grid and improving power quality. It provided an effective method reference for technological progress in related fields such as power electronics and control engineering.

This survey presents an in-depth exploration of two innovative designs of phase frequency detectors (PFDs): Non-Linear PFD (NLPFD), composite PFD. PFDs play a crucial role in phase-locked loops (PLLs), frequency synthesis circuits, frequency demodulators, AM radio receivers, etc. This works focuses on measuring the performance parameters such as blind zone, dead zone, detection range, reset delay, number of transistors utilized, power consumption, maximum operating frequency, and area. Through a comprehensive analysis, a light has been shed on the significance of these designs in advancing the capabilities of PLLs and frequency synthesis circuits. In this study also discusses the techniques to mitigate PFD parameters such as dead zone, blind zone. Finally, this paper concludes with the analysis of PLL using LPFD, NLPFD, and composite PFD architectures.

As the boost of power electronics technology, the harmonic problem in the power system is becoming increasingly prominent. Fourier decomposition is performed on the load current in the power system, and components with a frequency that is an integer multiple of the fundamental wave are referred to as harmonic components. Harmonic control is essential to establish a safe and reliable power grid environment and provide high-quality and clean electricity to power users. The study focused on parallel active power filters, proposed a specific harmonic detection method on the grounds of synchronous harmonic rotating coordinate system, and developed a phase-locked loop design on the grounds of order generalized integrator. Meanwhile, a compensation current control method on the grounds of space vector pulse width modulation was introduced. The results showed that in the full compensation simulation experiment, the compensated A-phase grid side current waveform was significantly improved and presented a sinusoidal shape. After 0.05 s, the actual output compensation current closely followed the command current. Meanwhile, after compensation, the total harmonic distortion rate decreased from 26.58 to 3.06%. In specific harmonic compensation simulation experiments, when the sum of 5th, 7th, and 11th harmonic components was used as the command current for compensation, the distortion of the current waveform was improved after the load undergoes a sudden change. After compensation, the 5th, 7th, and 11th harmonic content significantly decreased, and the total harmonic distortion rate decreased to 4.08%. This indicated that the proposed phase-locked loop design and harmonic detection method for active power filters had high stability and effectiveness. The study's primary contribution is to enhance the utilization efficiency of DC voltage and improve the dynamic response ability of current. Additionally, it offers a new method for reducing the impact of harmonics on the power grid and improving power quality. It provided an effective method reference for technological progress in related fields such as power electronics and control engineering. [ABSTRACT FROM AUTHOR]

This paper presents a new process, voltage and temperature (PVT) tolerant 7-stage ring type current starved voltage-controlled oscillator (CS-VCO). In this, a 7-stage ring VCO is proposed using power gated technique for phase locked loop (PLL) application. PLL plays a major role in clock and data recovery, Global Positioning System (GPS) system and satellite communications. For the high-speed application of PLL it is designed using 7-stage inverter delay cell with MOS current mode logic (MCML) technique. The circuit undergoes process, voltage and temperature variations with different parameters such as average power, oscillation frequency, phase noise, tuning range and output noise. The Monte-Carlo analysis justifies the proposed design provides better results. The circuit is simulated under 45 nm CMOS technology using cadence virtuoso. The average power consumption of the proposed circuit is 29.368 µW with the oscillation frequency of 3.06 GHz. The output noise and the phase noise of the proposed VCO are -161.55 dB and -125.92 dBc/Hz respectively. It achieves the frequency tuning range (FTR) of 95.09 %. The obtained simulation results are highly robust with PVT making the circuit suitable for PLL application. [ABSTRACT FROM AUTHOR]

Fast settling phase locked loops (PLLs) play a pivotal role in many applications requiring rapid attainment of a stable frequency and phase. In modern communication standards, these PLLs are extensively utilized to guarantee precise compliance with dynamic resource allocation requirements. In processors, these PLLs manage dynamic voltage frequency scaling. Moreover, the fast-settling PLLs expedite the scanning of frequency spectra in sophisticated electronic radar set-ups, proving particularly advantageous for imaging and scanning radar applications. The rapid response exhibited by these PLLs is also harnessed in quantum technologies, catering to the urgent need for precise frequency adjustments to manipulate qubit states effectively. The strategies employed to attain fast-settling PLLs are primarily classified into five broad techniques in this article: enhanced phase frequency detection, hybrid multiple subsystems, VCO start-up, gear shift, and look-up table or finite state machine. This article explores the fundamental operational principles encompassing these techniques and presents optimal settling times for each method reported in the literature. Finally, the architectures utilizing these techniques will be evaluated based on their figure of merit (FoM), settling time, and tuning range. [ABSTRACT FROM AUTHOR]

Purpose: Vibration parameter estimation using a non-contact technique for industry applications, biomedical applications, condition monitoring of civil structures, and rotating machines. Methods: An alpha sliding window infinite Fourier transform (α SWIFT) based digital phase-locked loop (DPLL) is proposed to measure the vibration signal. The proposed DPLL is mainly comprised of a quadrature detector, which is derived from the α SWIFT structure, a moving averager unit, a controller unit, and a bi-quad oscillator. The α SWIFT structure provides inherent stability as the system poles always lie inside the unit circle and has high noise rejection capability due to narrow bandwidth at high values of time-constant. Further, the α SWIFT structure works on an exponential window function that gives higher weight to recent samples and also reduces the leakage effects. The Pareto front multi-objective particle swarm optimization (PF-MOPSO) algorithm is introduced in the DPLL for computing the controller gains. Three non-conflicting objective functions, namely amplitude error, phase error, and total harmonic distortion (THD) are considered in the PF-MOPSO algorithm to optimize the controller parameters. The bi-quad oscillator generates the variable pulses based on the extracted signal to synchronize the remaining units. Results: The proposed DPLL is able to extract the multi-frequency components of the vibration parameter using a non-contact technique. The system is capable of measuring low frequencies up to 0.2 Hz and low amplitudes up to 0.06 mm. The proposed DPLL can also extract the vibration parameters up to the noise level of - 2 dB. [ABSTRACT FROM AUTHOR]

Summary: This paper proposes a fractional delay (FD) Newton structure for Lagrangian interpolation in single phase grid integrated photovoltaic (PV) system. The structure has been designed for achieving shunt compensation and as a phase locked loop circuit for synchronization. The designed controller performs multiple tasks of feeding the active power to meet the load demand and simultaneously providing reactive power compensation, power factor improvement, and compensating other power quality voltage and load current harmonics. Further, synchronization poses a severe challenge in integrating the PV power electronic converters to the grid. The FD filter is used to discretize the continuous time signal at any time instant using interpolation algorithm employing the non‐integral value of the sampling rate delays. The FD delay filter is made adaptive and self‐learning by using least mean square algorithm. The designed synchronization technique meets the objective of faithfully tracking the phase of the grid voltage under all grid disturbances such as under voltage, overvoltage, frequency variations, and phase angle disturbances in a precise manner. [ABSTRACT FROM AUTHOR]

This paper comprehensively investigates how the control voltage settles in Voltage Controlled Oscillators (VCO) by considering all non-ideal factors in phase lock loop circuits. Also, the different structures of the phase detector and their effect on the locking speed of the phase-locking loop circuit, the control voltage ripple and the locking frequency range will be compared. Three phase locked loop circuits with XOR detector, RS-FF detector and dynamic phase detector were investigated in this paper. The simulations were performed on 0.18 µm-CMOS technology with a 1.8V power supply. The simulation results show that the operating range of the phase-locked loop circuit including dynamic phase detector with charge pump circuit has less ripple for the non-ideal effects compared to the phase-locked loop circuit including XOR phase detector and the phase-locked loop circuit including RS-FF phase detector. of the phase-locked loop circuit including dynamic phase detector is designed using 180nm CMOS technology and the simulation results show that for a supply voltage of 1.8V, frequency range is 0.284-3.33GHz, power consumption is 2.86mW and phase noise is -118.8dBc/Hz.

Synchronization of single-phase inverters is a challenging task due to the difficulty of deriving a rotating voltage frame, in the absence of adequate information from the other two phases. Moreover, modern standards, such as the fault ride-through (FRT) directives, require inverter-based distributed generators (IBDGs) to respond as fast as possible to grid disturbances; thus, it is necessary to rely on accurate and fast synchronization algorithms. The scope of this paper is to propose a new synchronization technique, which satisfies three important requirements: a) fast dynamic response, b) adequate double frequency rejection, c) low computational complexity. Our synchronization technique is a flexible method relying on variable-length transfer delay, which calculates network frequency by analyzing voltage angle differentials. To enhance this differentiation process and address potential discontinuities, we introduce Heaviside-based functions. Both simulations conducted in MATLAB/Simulink and experimental trials demonstrate that our proposed synchronization method outperforms the most widely adopted existing techniques in terms of dynamic response and computational efficiency. Due to its excellent dynamic performance, the proposed method can offer a stable FRT capability, with fast detection of the voltage dips and seamless resynchronization following fault clearance, all while preventing DC-link overvoltage issues.

The presented fast-locking phase-locked loop (PLL) approach, driven by sliding mode control (SMC), aims to maintain defined design parameters and system stability while achieving faster frequency switching. By adding the SMC output control voltage to the tuning terminal of the voltage controlled oscillator (VCO), the PLL system achieves a higher absolute rate of change of the VCO output frequency during frequency hopping. Simulation results in Simulink demonstrate a significant reduction in locking time, from $40~\mu \text {s}$ in the conventional PLL to $5~\mu \text {s}$ in the proposed PLL, under identical conditions of loop bandwidth and charge pump current.

This paper presents an improved sensorless controller scheme for a robust permanent magnet synchronous motor. Firstly, a sliding mode observer based on a variable rate approach rate is designed to observe the back electromotive force, enhance the robustness of the back electromotive force acquisition process, and reduce the system buffeting. Secondly, the concept of finite control set model predictive control is introduced, and the position angles are divided into small angles to form finite control sets. Then the position Angle of the finite control set is entered into the sliding mode observer to calculate the back electromotive force. At the same time, the optimal position angle is obtained based on the cost function of the back electromotive force. In order to reduce the number of iterations, the dichotomy is adopted to reduce unnecessary calculations. The proposed finite position-set phase-locked loop (PLL) avoids the PI controller in the traditional PLL and further improves the robustness of the system. Finally, the effectiveness of the proposed scheme is verified by relevant experiments.

The reliability of online monitoring device for metal oxide arrester (MOA) is the prerequisite for ensuring the MOA normal operation. For online monitoring device, this paper proposes the non-destructive calibration scheme which can improve maintenance efficiency. The on-site calibration device consists of current source, ammeter, micro-current detector and control unit. There are two key technologies involved in the on-site calibration device, the one is the phase locked loop (PLL) for current source, the other is the high precision current detection for ammeter and micro-current detector. The proposed PLL of the reference voltage can generate low delay orthogonal signals and eliminate the second harmonic disturbances caused by the crystal oscillator error of microcontroller unit (MCU). The experimental results show the effectiveness of the proposed calibration scheme.

In industrial electronic equipment or communication equipment, a reference clock should be generated for stable operation of the equipment, which requires precise and stable reference frequency generation. As a method for generating this reference frequency, an analog method called PLL (phase locked-loop) has been devised and widely used. However, in order to make a more precise and stable reference frequency simple and economical, a DDS (direct digital synthesizer) has been developed. In this paper, we propose a stable and accurate method to generate a low frequency of the PWM method via pure logic circuit configuration without a microprocessor for digital reference frequency generation. Depending on the electronic communication equipment, the required reference frequency varies from a low frequency to a very high frequency. The reference frequency synthesis required in these frequency bands has been studied in various ways, but in industries such as railways, the low-frequency band based on the DDS method is used. In particular, it is very important to operate without a single operating error or failure in order to obtain information for stopping the train. Therefore, it is necessary to design a pure logic method that excludes a stored program type processor that minimizes the possibility of temporary interruption due to disturbance such as surge or high voltage. Therefore, through this study, the algorithm is implemented so that the duty ratio is output at 50:50, the circuit is configured so that two target frequencies are generated at the same time, and the performance is verified by generating the low-frequency band used for stopping the railway train. It was confirmed that the accuracy and stability were improved compared to the analog method used for stopping the railway train, and it was verified that the frequency resolution was superior to the similar results obtained in the digital frequency synthesis field so far. [ABSTRACT FROM AUTHOR]

A differential ring CMOS voltage-controlled oscillator (VCO) with dual-delay path topology is proposed in this paper. In this work, the focus area is to improve the tuning range of VCO and phase noise performance of the VCO. The dual-delay path topology is used with P-MOS as load in series with negative-skewed delay transistors. This design gives the wider tuning range and this increases the phase noise performance of the VCO. After the post-layout simulation, frequency tuning range and power dissipation range are 730 MHz to 2.81 GHz and from 1.32 mW to 4.62 mW respectively. The phase noise for this VCO is −97.35 dBc/Hz at 1 MHz offset. The technology used in this work was taken from the library of SCL 180 nm technology. This design exhibits excellent phase noise performance. [ABSTRACT FROM AUTHOR]

Copyright of Electric Machines & Control / Dianji Yu Kongzhi Xuebao is the property of Electric Machines & Control and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

In this paper, a customizable low-cost voltage waveform generator based on a real-time desktop PC and embedded data acquisition card synchronized with Coordinated Universal Time (UTC) is presented. A software approach to phase-locked loop synchronization with an external Global Positioning System (GPS) pulse signal is utilized to achieve a time uncertainty of ± 1 μ s. This avoids expensive hardware modules for synchronization and timing purposes, which are commonly presented in literature. Besides the application for controlling the test platform, our own phasor data concentrator (PDC) application is running concurrently on the host PC. The latter is used for collecting and comparing the syncrophasor data from the test platform against the syncrophasor data measured by phasor measurement units (PMUs) under the test. The paper describes all procedures for generating reference test signals. Numerous case studies were performed, and experimental results for steady-state compliance as well as frequency ramp and phase modulation tests for dynamic compliance are presented in detail. All tests confirm that customizable test platform meets the requirements of IEEE/IEC standards. Compared to other calibrators, the cost as well as the specifications and point-by-point concept of data processing makes the described test platform suitable for performance analysis of PMU algorithms implemented on various development boards. [ABSTRACT FROM AUTHOR]

The high‐frequency circuits used in communication systems significantly depend on the functioning of the Phase‐Locked Loop (PLL). The power consumption is traded with the performance in the high‐frequency PLL. The proposed robust Phase and Frequency Detector (PFD) has multiple benefits of low‐power and reliable functioning at high frequency. The PFD highly contributes to the stable performance of the PLL, and this work proposes a 10T PFD for low‐power. The proposed PFD employs Gate Diffusion Input (GDI) logic based D‐flip flop and the pass transistor logic in the reset path to reduce power consumption. The PFD uses only 10 transistors, enabling a faster reset path and consuming less power at high frequencies. The 10T PFD was designed using 90 nm CMOS PDKs and simulated using CADENCE Specter for functional verification and performance analysis. The 10T PFD achieved a reset time of 61.4 ps at 3 GHz alongside a power consumption of 189.2 nW. Also, the overall power consumption of PLL using the proposed PFD at 3 GHz was 103.2μW demonstrating the effectiveness of 10T PFD over other conventional PFDs. [ABSTRACT FROM AUTHOR]

This research designs a robust time–frequency signal generation system based on the composite atomic clock onboard a navigation satellite, which focuses on the atomic timescale (ATS) generation algorithm and the paper time steering technology of physical realization signal. Combined with the improved ATS algorithm of weighted Kalman, we use the precise clock error data of Center for Orbit Determination in Europe to calculate the single-satellite paper time with higher stability than the classical ALGOS algorithm as a reliable steering reference. The cost function combined with genetic algorithm is designed, and a strategy for optimizing the parameters of the Kalman equivalent digital phase-locked loop control system through adaptive iterative optimization is proposed to obtain the optimal steering value with greatly improved precision. Simulations show that with the improved composite paper time obtained by the single-satellite atomic clock group set as the reference, the time steering error of the steered signal can be maintained within ± 0.09 ns, and the long-term stability is 4.84E−15/1 day. Compared to the single master-clock and ALGOS scheme, respectively, the time steering error is reduced by 58% and 26%, and the frequency stability at 10,000 s is improved by 47% and 15%. Study results provide scheme support for frequency stability performance improvement and reliable application of single-satellite autonomous timekeeping. [ABSTRACT FROM AUTHOR]

In this work, an optimal phase locked loop (PLL) is employed to estimate the fundamental grid frequency and phase angle under grid disturbances, which largely reduces the frequency and phase error. Conventional synchronous reference frame (SRF) offers considerable results for balanced grid conditions but has poor performance under grid disturbances with improper phase detection. In this regard, gravitational search algorithm (GSA)‐based optimization is utilized to optimally tune the proportional and integral (PI) gain values of conventional SRF PLL, which ensures the proper tracking of fundamental phase angle and frequency even during abnormal grid conditions, that is, voltage unbalance, frequency variations, high‐frequency harmonics, and phase variations. Further, integral square error (ISE) criteria, settling time, and overshoot are considered as objective functions to obtain the optimal value of current gain, present in the control loop of a grid‐tied solar photovoltaic (PV) system. The supremacy of the proposed work, compared to SRF and optimal SRF PLL, is tested with MATLAB®/Simulink studies and verified by dSPACE‐1104‐based hardware‐in‐loop (HIL) results for real‐time validation. [ABSTRACT FROM AUTHOR]

Transient synchronization stability is the precondition for dynamic reactive power compensation of STATCOMs in the event of a grid fault, which might be so serious that their neighboring distributed power generators lose their synchronization stability. However, there are very limited research publication in this area. This paper focuses on STATCOM synchronization stability and its improvement. The proposed adaptive phase locked loop (PLL) is based on the estimated phase error rather than the estimated frequency error, which is an innovative approach not yet been seen in published papers. Moreover, the impacts of short-circuit ratio and the ratio of equivalent grid R to X are also investigated. Both steady-state analysis and time-domain simulation results are presented in this paper. The results show good consistency between steady-state analysis, simulation with a controlled current source model and with a detailed STATCOM model, and the differences are within reasonable range. Compared with the typical PLL, the proposed adaptive PLL demonstrates improved performance of transient synchronization stability.

Copyright of Electric Machines & Control / Dianji Yu Kongzhi Xuebao is the property of Electric Machines & Control and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

In this paper, a very low spur 5.9-GHz integer-N frequency synthesizer designed for a Cellular Vehicle-to-Everything (C-V2X) receiver is presented. The PLL is referenced to a 10-MHz crystal oscillator and the design is implemented in a 65-nm CMOS process. The output of the synthesizer has differential quadrature topology and provides the local oscillator signal to a downconverter mixer of C-V2X receiver. Post-layout simulations show that the reference spurs are better than −88 dBc through loop sampling technique which was implemented in a 11.8-GHz VCO design for the first time to the best of our knowledge. The best spur level without the loop sampling technique applied is limited to −55 dBc. Using the loop sampling technique provides a spur reduction of 33 dB which is a significant improvement at this frequency. Based on post-layout simulations, the design has a phase noise of −97/−99/−114 dBc for 10 kHz/100 kHz/1 MHz frequency offsets, respectively, which presents competitive numbers with the designs in the literature. The design has 1.2-V nominal supply voltage for the analog and digital blocks. The total power dissipation of the synthesizer core is 6 mW from a 1.2-V supply while the output buffers driving a 100-fF load consumes 18 mW. [ABSTRACT FROM AUTHOR]

Recently, there has been a huge advancement in renewable energy integration in power systems. Power converters with grid-forming or grid-following topologies are typically employed to link these decentralized power sources to the grid. However, because distributed generation has less inertia than synchronous generators, their use of renewable energy sources threatens the electrical grid’s reliability. Suitable control approaches for ensuring frequency and voltage stability in the grid-connected form of operation are established in this study, which offers dynamic, seamless power switching in the islanded mode of operation. In this research, effective Phase Locked Loop (PLL) techniques for grid-forming (GFM) and grid-following (GFL) converters are designed to achieve a smooth transition from grid-tied to islanded mode of operation. In this work, PLL configurations are implemented while considering the active and reactive power, frequency, voltage, and current parameters of the system, and ensuring voltage and frequency stability. The simulation results in a microgrid network that ensures a smooth transition of power transfer while switching between modes of operation, and supports the voltage and frequency stability of the system.

Electric vehicles (EVs) are a promising solution to reduce carbon dioxide (CO2) emissions, but this reduction depends on the fraction of renewable sources used to generate electricity. Wind energy is thus a vital candidate and has experienced a remarkable surge recently, establishing itself as a leading renewable power source worldwide. The research on Direct-Driven Permanent Magnet Synchronous Generator (PMSG)-based type 4 wind farms has indicated that the Phase-locked Loop (PLL) bandwidth significantly impacts Sub-Synchronous Resonance (SSR). However, the influence of PLL architecture on SSR remains unexplored and warrants investigation. Therefore, this paper investigates PLL architectural variations in PLL Loop Filter (LF) to understand their impact on SSR in type 4 wind farms. Specifically, an in-depth analysis of the Notch Filter (NF)-based enhanced PLL is conducted using eigenvalue analysis of the admittance model of a PMSG-based type 4 wind farm. The findings demonstrate that the NF-based enhanced PLL exhibits superior performance and improved passivity in the sub-synchronous frequency range, limiting the risk of SSR below 20 Hz. Additionally, Nyquist plots are employed to assess the impact on system stability resulting in increased stability margins. In the future, it is recommended to further investigate and optimize the PLL to mitigate SSR in wind farms. [ABSTRACT FROM AUTHOR]

In this paper, we present the high-speed phase frequency detector where the phase characteristics are enhanced. This PFD has a simple structure where the dead zone is annihilated and blind zone is highly reduced. This PFD generates UP and DN signal only when it gets the distinct phase difference. With the reduction of the reset time, the proposed PFD function is in the order of 1.5 M H z − 4 G H z operating frequency. The design shows the improvement by completely eliminating the dead zone. However, the blind zone is minimised to 74.6 p s in the phase characteristics which improves the output phase noise as −132.9 d B c / H z at 1 M H z offset frequency. The power consumption is minimised upto 417.3 μ W @ 4 G H z operating frequency. The design is simulated in standard 0.18 \mum CMOS technology node with 1.8 V power supply. Furthermore, the achieved frequency band is applicable for high-speed and low-power PLL application such as Zigbee, Wifi, Bluetooth and 4 G communication. [ABSTRACT FROM AUTHOR]

This paper presents a systematic control scheme for a wind energy conversion system with variable speed and describes a permanent magnet synchronous generator PMSG with five phases. The machine employs back-to-back converters, while the grid-side converters are used. Stator current and mechanical rotation speed control are employed to accomplish maximum power point tracking operation on the machine side converter at wind speed below the rated speed. The pitch of the angle is used to limit the extracted wind energy when the wind surpasses the specified wind. The grid current control loop regulates both active and reactive power injection at the unity power factor for the grid side converter. The fivephase PMSG rotor speed is controlled by the twisting sliding mode controller in order to maintain the reference speed in various wind speeds. Performance comparisons between the twisting sliding mode controller, conventional proportional integral controller, and integral sliding mode controller show that the twisting sliding mode controller is superior to the other controllers in steady state error. According to this study, the overall efficiency is increased to 94% when using the TSMC controller rather than the ISMC and PI controllers, which are currently at 92.45% and 88.12% respectively. MATLAB/Simulink simulation results are used to verify the effectiveness of the suggested control technique. [ABSTRACT FROM AUTHOR]

Synchronization is a critical aspect of integrating renewable energy sources and inverter-based power plants into the electrical grid. Phase-Locked Loops (PLLs) are widely used for this purpose, providing rapid and accurate phase and frequency estimation. In PLLs, the Moving Average Filter (MAF) is commonly employed to extract the fundamental grid voltage component, particularly in the presence of harmonic distortions. Traditional PLLs with a full-cycle time-window MAF perform well in grids with sinusoidal voltage waveforms and DC offsets. However, this approach sacrifices the speed of dynamic response due to the extended time window. In this paper, we introduce a novel approach to address this trade-off. Our method involves reducing the MAF’s time window to one cycle by incorporating a delay operator, effectively reducing model complexity and runtime by 50%. Through comprehensive simulations and experimental scenarios, we demonstrate the practical advantages of the proposed method. Comparison of the proposed approach is provided with existing algorithms in the literature, which illustrate its effectiveness in terms of mitigating PLL oscillations in the presence of DC offsets and other non-ideal grid conditions while achieving a 50% improvement in the execution speed. Therefore, the contribution of this paper is in the field of grid synchronization by providing a balanced solution that enhances dynamic response without compromising DC-offset rejection. The proposed method can improve the stability and efficiency of grid-connected systems involving renewable energy sources and inverter-based power plants.

In this article, one of the most recent multilevel converter topologies named packed U-cells is developed for three-phase grid-connected inverter mode using photovoltaic input voltage sources. This topology makes a very important research subject in what concerns the adaptation of multilevel inverters with photovoltaic systems. According to the literature, it is well applicable with the string type and suitable for high-voltage applications because the number of switches is less than conventional topology and maximum blocking voltage is Udc and 2 Udc ; however, it is not applicable for multistring type and unsuitable for the central type because it is based on isolated DC source. The packed U-cells topology is highly optimized from the point of view of the number of passive and active components. The output voltages of our converter are composed by seven levels obtained by the auxiliary buses voltages regulation. In order to obtain the DC input voltages of 120 V for the inverter, photovoltaic generators are connected to a boost converters. The maximum power point tracking method based on the Perturb and Observe was used to improve and optimize the performance of the photovoltaic system control in the simulation part. The grid-connected PUC7 inverter operates with a unit power factor and injects active power into the grid. The control is configured to make the current waveform in phase with the AC voltage waveform. Reference angle variations have been made to operate with different power factors to test the performance of the applied control and the influence of these variations on the auxiliary buses voltages regulation. The simulations were done under Matlab/Simulink platform and have been experimentally verified using dSpace 1104 controller board and three-phase packed U-cells inverter composed by nine half-bridge insulated-gate bipolar transistor modules. [ABSTRACT FROM AUTHOR]

This paper presents a systematic control scheme for a wind energy conversion system with variable speed and describes a permanent magnet synchronous generator PMSG with five phases. The machine employs back-to-back converters, while the grid-side converters are used. Stator current and mechanical rotation speed control are employed to accomplish maximum power point tracking operation on the machine side converter at wind speed below the rated speed. The pitch of the angle is used to limit the extracted wind energy when the wind surpasses the specified wind. The grid current control loop regulates both active and reactive power injection at the unity power factor for the grid side converter. The five-phase PMSG rotor speed is controlled by the twisting sliding mode controller in order to maintain the reference speed in various wind speeds. Performance comparisons between the twisting sliding mode controller, conventional proportional integral controller, and integral sliding mode controller show that the twisting sliding mode controller is superior to the other controllers in steady state error. According to this study, the overall efficiency is increased to 94% when using the TSMC controller rather than the ISMC and PI controllers, which are currently at 92.45% and 88.12% respectively. MATLAB/Simulink simulation results are used to verify the effectiveness of the suggested control technique.

Phase locked loop (PLL) circuits are widely used in fractional frequency synthesizers. In these synthesizers, fractional multiples of the reference frequency can be synthesized, so the reference frequency and the bandwidth of the loop can be increased. This frequency synthesizer is commonly used due to its flexibility and convenient frequency adjustment. In this paper, a PLL circuit of the transistor level is designed in which a hybrid digital sigma-delta modulator with reduced hardware is used. This Digital Delta-Sigma Modulator (DDSM) has four stages that have a lower noise level and power consumption than the conventional type. This PLL circuit has a third-order loop filter and a voltage-controlled oscillator of the NMOS type. In the PLL circuit, two counters are used in its feedback path. In the proposed divider, there is a dual divider P / P + 1 (in this case 5, 6) which divides its input signal by 5, 6 according to the control input. A design example for the PLL is provided. A third stage digital Delta-Sigma modulator with reduced hardware is also used to control these counters. This modulator has less power consumption than the conventional method and has less number of transistors by 85%.

High-sensitivity carrier phase tracking is essential for new GNSS high-precision applications such as unmanned vehicles and smartphones. Increasing coherent integration time is the primary way to improve the sensitivity of carrier phase tracking, which is, however, significantly restricted by the receiver local oscillator instability. We propose a long coherent integration (LCI) architecture to improve carrier phase tracking. The architecture is equipped with a multichannel cooperative loop to track receiver oscillator errors and local loops to perform super-long coherent integration periods. The transfer function of LCI tracking loops is established in s-domain, and the tracking error models induced by thermal noise and Allan deviation oscillator phase noise are derived in z-domain. The performance of the LCI tracking architecture is tested through both simulation and actual GNSS signals. The proposed error models of LCI are validated through the semi-analytic simulation. Both simulation and real signal testing results indicate that LCI tracking loops can perform coherent integration up to 3 s and track extremely weak signals of 6 dB-Hz with carrier phase accuracy of around 4 degrees. [ABSTRACT FROM AUTHOR]

A technique to create a temperature insensitive area on a die using an integrated micro-heater and a phase-locked loop (PLL) configuration is described. The proposed PLL configuration employs thermal feedback through the micro-heater to significantly improve the temperature stability of the die area. Two oscillators employed in the PLL act as temperature sensors to detect the ambient temperature variations and command the thermal loop to compensate it. The temperature stability of these oscillators located in the temperature-compensated die area is improved significantly and can provide a stable timing signal needed for the system. Design methodologies and system-level analysis are presented, and a test-chip for proof-of-concept is designed and fabricated using a standard 130 nm CMOS technology. Analysis and experimental results show that micro-heating provides a low pass filtering effect such that the loop filter and charge pump can be eliminated from the PLL system. Test characterization of the realized proof-of-concept chip shows that the temperature stability of the die area can be improved by a factor as large as 50 × for an ambient temperature range of 36–52 °C. It is shown by simulation that this range can be improved by many folds using SOI CMOS instead of bulk CMOS. [ABSTRACT FROM AUTHOR]

In the literature history, many enhanced phase locked loops (PLLs) have been presented to enhance the performance of synchronous reference frame-PLL (SRF-PLL) against the grid imbalances and disturbances. One of these methods is a dual second order generalized integrator-PLL (DSOGI-PLL), which provides a perfect imbalance rejection capability. However, the DSOGI-PLL has a large convergence time and frequency overshoot, which brings a serious problem for grid-connected equipments. The aim of this study is to improve the performance of standard DSOGI-PLL without decreasing its disturbance rejection capability. In accordance with this purpose, a simple yet effective method is proposed. The effectiveness of advanced DSOGI-PLL is verified by experimental results.

As one of the state-of-the-art grid voltage synchronization techniques, Quasi-type-1 structure based phase locked loop (QT1-PLL) achieves an excellent detection performance when only odd-order harmonics needs to be eliminated by Moving average filter (MAF). Nonetheless, when it is necessary for MAF to eliminate the fundamental negative sequence component, more delay will be introduced to the PLL, reducing its stability. The transient response speed of QT1-PLL needs to be reduced to ensure stability, which may be unacceptable for grid-connected power converters. To deal with this situation, this paper proposes a cascaded filtering stage with small delay. The suggested filtering stage is composed of second-order lead compensator, notch filter, first-order lead compensator and MAF, which is integrated in QT1-PLL. Compared with the traditional QT1-PLL, the proposed PLL has faster transient response speed and higher detection accuracy. The simulation and experimental results verify the effectiveness of the suggested filtering stage.