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By utilizing the fringing electric field from the control gate of cells in NAND flash memory string, the source/drain in the cells could be removed, which improves cell scalability and gives very positive effects. In this scheme, cells with underlapped S/D or localized buried oxide in the space shown more reasonable read current characteristics. For NOR flash memory, cells with recess channel structure have studied. We demonstrated successful operation of 4-bit/cell using the recess structure and found no interference in a cell and adjacent cells. Finally, we compared measured RTN in FinFET SONOS and saddle SONOS devices. The current fluctuation of the FinFET devices is higher by ~3 times than that in the saddle devices. We expect that our approach is very promising for future high density and high performance flash memory technology.

We have analyzed program inhibition in bulk fin SONOS flash memory devices with a variation of fin body width. Compared to the coupled channel potential of wide fin channel device during programming, the potential of narrow fin structure device was much large. Relationship between the fin width and the program disturbance characteristics can be useful in memory design and optimization.

High pressure deuterium annealing was applied to nano-scale CMOS devices which has Plasma Nitride Oxidation (PNO) gate oxide. The annealing effect was characterized in terms of different sizes, charge pumping, hot carrier and NBTI stress, and \/f noise for the first time. The characteristics of NMOS were improved by the annealing. But PMOS has only improved NBTI characteristic. Devices with narrow channel width shown more significant effect than wide channel devices.