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Spin Orbit Torque Magnetic Random Access Memory (SOT–)MRAM is gaining interest as it eradicates several limitations posed by its predecessor Spin Transfer Torque (STT-)MRAM, yet inherits all its advantages. This work explores in detail, the suitability of SOT–MRAM implemented caches in different levels of memory hierarchy in comparison to conventional SRAM technology, over several performance parameters like area, energy consumption and execution time for an embedded benchmark suite. Our circuit-level analysis shows that SOT–MRAM outperforms SRAM for caches (>128 KB), and only lags in area and read-access energy for smaller caches. A typical 512 KB SOT–MRAM cache improves area by 1%, read/write latency by 33/38%, and leakage by over 99% than that of SRAM memory technology. The architecture-level analysis confirms that on average SOT–MRAM is energy efficient by 74% in L1, 97.2% in L2 and 89.3% in both (i.e., L1 + L2) implementations against SRAM, for a 22nm technology node. We also estimate that SOT–MRAM only solution offers ∼68.8% energy savings and ∼79.5% better EDP than Hybrid (L1-SRAM and L2-SOT) memory hierarchy for multi-core ARM processors. [ABSTRACT FROM AUTHOR]

High-performance edge artificial intelligence (Edge-AI) inference applications aim for high energy efficiency, memory density, and small form factor, requiring a design-space exploration across the whole stack—workloads, architecture, mapping, and co-optimization with emerging technology. In this article, we present a system-technology co-optimization (STCO) framework that interfaces with workload-driven system scaling challenges and physical design-enabled technology offerings. The framework is built on three engines that provide the physical design characterization, dataflow mapping optimizer, and system efficiency predictor. The framework builds on a systolic array accelerator to provide the design-technology characterization points using advanced imec A10 nanosheet CMOS node along with emerging, high-density voltage-gated spin-orbit torque (VGSOT) magnetic memories (MRAM), combined with memory-on-logic fine-pitch 3-D wafer-to-wafer hybrid bonding. We observe that the 3-D system integration of static random-access memory (SRAM)-based design leads to 9% power savings with 53% footprint reduction at iso-frequency with respect to 2-D implementation for the same memory capacity. Three-dimensional nonvolatile memory (NVM)-VGSOT allows $4\times $ memory capacity increase with 30% footprint reduction at iso-power compared with 2-D SRAM $1\times $ . Our exploration with two diverse workloads—image resolution enhancement (FSRCNN) and eye tracking (EDSNet)—shows that more resources allow better workload mapping possibilities, which are able to compensate peak system energy efficiency degradation on high memory capacity cases. We show that a 25% peak efficiency reduction on a $32\times $ memory capacity can lead to a $7.4\times $ faster execution with $5.7\times $ higher effective TOPS/W than the $1\times $ memory capacity case on the same technology.

Herein, the impact of postdeposition annealing on resistive switching behavior of radio frequency magnetron sputtered WO3 thin films is reported. Films are deposited under glancing angle deposition (GLAD) configuration of sputtering at varying GLAD angle from 65° to 80°. Structure transition from monoclinic to orthorhombic phase in deposited WO3 films is perceived after ex situ annealing at temperature of 400 °C. Resistive switching properties show shift from bipolar to unipolar switching on postdeposition annealing. WO3 films show unipolar switching behavior after ex situ annealing for all prepared samples. The value of resistance in high resistance state is lowered after ex situ heating treatment and interestingly switching voltage also reduces to 3 V from 7 V after annealing treatment. The ratio of high to low resistance state for annealed WO3 film fabricated at 70° GLAD angle is achieved to be maximum (≈219). A detailed charge transport mechanism shows that ohmic behavior is dominant current conduction mechanism at lower applied voltage, while space charge limited current and Child's law are dominant at higher applied voltages. Obtained results encourage utilization of prepared WO3 thin films toward a wide variety of applications in optoelectronics, microelectronics, and environmental engineering along with advanced electronics such as resistive memory devices. [ABSTRACT FROM AUTHOR]

Harnessing multibit precision in nonvolatile memory (NVM)‐based synaptic core can accelerate multiply and accumulate (MAC) operation of deep neural network (DNN). However, NVM‐based synaptic cores suffer from the trade‐off between bit density and performance. The undesired performance degradation with scaling, limited bit precision, and asymmetry associated with weight update poses a severe bottleneck in realizing a high‐density synaptic core. Herein, 1) evaluation of novel differential mode ferroelectric field‐effect transistor (DM‐FeFET) bitcell on a crossbar array of 4 K devices; 2) validation of weighted sum operation on 28 nm DM‐FeFET crossbar array; 3) bit density of 223Mb mm−2, which is ≈2× improvement compared to conventional FeFET array; 4) 196 TOPS/W energy efficiency for VGG‐8 network; and 5) superior bit error rate (BER) resilience showing ≈94% training and 88% inference accuracy with 1% BER are demonstrated. [ABSTRACT FROM AUTHOR]

In this article, the impact of interfacial fixed charges on the memory window (MW) of HfO2-based ferroelectric field-effect transistor (FeFET) is investigated using technology computer-aided design (TCAD) device simulations. We have considered the presence of fixed charges at the interface between the ferroelectric layer (FE) and the interlayer dielectric (IL) of FeFET with metal/ferroelectric/interlayer/Si (MFIS) gate structure. Our study indicates that the presence of fixed charges affects the polarization and corresponding depolarization field in the ferroelectric. Positive and negative interface charges can align the polarization direction. The MW degradation is observed with the increase in the fixed charge concentration (Qf).

Harnessing multibit precision in nonvolatile memory (NVM)‐based synaptic core can accelerate multiply and accumulate (MAC) operation of deep neural network (DNN). However, NVM‐based synaptic cores suffer from the trade‐off between bit density and performance. The undesired performance degradation with scaling, limited bit precision, and asymmetry associated with weight update poses a severe bottleneck in realizing a high‐density synaptic core. Herein, 1) evaluation of novel differential mode ferroelectric field‐effect transistor (DM‐FeFET) bitcell on a crossbar array of 4 K devices; 2) validation of weighted sum operation on 28 nm DM‐FeFET crossbar array; 3) bit density of 223Mb mm−2, which is ≈2× improvement compared to conventional FeFET array; 4) 196 TOPS/W energy efficiency for VGG‐8 network; and 5) superior bit error rate (BER) resilience showing ≈94% training and 88% inference accuracy with 1% BER are demonstrated.

This work paves the way to realize a processing-in-pixel (PIP) accelerator based on a multilevel HfOx resistive random access memory (RRAM) as a flexible, energy-efficient, and high-performance solution for real-time and smart image processing at edge devices. The proposed design intrinsically implements and supports a coarse-grained convolution operation in low-bit-width neural networks (NNs) leveraging a novel compute-pixel with nonvolatile weight storage at the sensor side. Our evaluations show that such a design can remarkably reduce the power consumption of data conversion and transmission to an off-chip processor maintaining accuracy compared with the recent in-sensor computing designs. Our proposed design, namely an integrated multilevel RRAM (HfOx)-based processing-in-pixel accelerator (MR-PIPA), achieves a frame rate of 1000 and efficiency of ~1.89 TOp/s/W, while it substantially reduces data conversion and transmission energy by ~84% compared to a baseline at the cost of minor accuracy degradation.

This paper investigates scaled ferroelectric field-effect transistor (FeFET) nonvolatile memories (NVMs) with high-k spacer device design considering ferroelectric-dielectric random phase variations with TCAD atomistic simulations. Our study indicates that, in addition to raising the orthorhombic phase and reducing the grain size of the ferroelectric, using high-k spacers can serve as another way to enhance the scalability of FeFETs because it improves both the mean memory window (MW) and the worst-case MW. More importantly, these improvements increase with the down-scaling of gate length. In addition, we have investigated the impact of high-k spacers on the critical electric field across interfacial layer ( $\text{E}_{\mathrm{ IL}}$ ) for the reliability of FeFET NVMs. Our study suggests that, for scaled FeFETs with high-k spacers, the highest $\text{E}_{\mathrm{ IL}}$ during write operation is no longer located near the S/D edge but at the mid channel. Using high-k spacers can reduce the mid-channel $\text{E}_{\mathrm{ IL}}$ , and the reduction increases with decreasing gate length due to the increasing impact of high-k spacers. Our study may provide insights for future high-density FeFET design.

Nowadays, field programmable gate arrays (FPGAs) have been widely adopted to serve as accelerators in artificial intelligence and big data related applications. Since the static random access memory (SRAM)-based FPGA is suffering from limited density and high leakage power, nonvolatile FPGAs have been proposed, where SRAM is replaced with emerging nonvolatile memories (NVMs). Multilevel cell (MLC), which can store multiple bits within one memory cell, further improves the density of nonvolatile FPGAs and shows great potential to enable large on-chip memory. However, it suffers from limited lifetime. In this article, we propose a wear leveling scheme to improve lifetime of MLC-based nonvolatile FPGAs. Instead of generating a series of configuration files for runtime reconfiguration, we propose to identify write-heavy MLC regions and dynamically transform them to durable single-level cell (SLC) mode. Specifically, we propose three modules: 1) pertaining to write behavior monitor; 2) approximate cost calculator; and 3) mode transformation manager to achieve adaptive mode transformations. We consider FPGA features to design these modules, which is different from implementations for MLC-SLC transformation in CPU architecture. Evaluation shows that the proposed scheme can improve lifetime for MLC nonvolatile FPGAs by $6.03\times $ , at cost of 12.5% storage overhead. [ABSTRACT FROM AUTHOR]

Existing nonvolatile memory (NVM)-based file systems can fully leverage the characteristics of NVM to obtain better performance than traditional disk-based file systems. It has the potential capacity to efficiently manage metadata and perform fast metadata operations. However, most NVM-based file systems mainly focus on managing file metadata (inode), while pay little attention to directory metadata (dentry), which also has a noticeable impact on the file system performance. Besides, the traditional journaling technique that guarantees metadata consistency may not yield satisfactory performance on NVM-based file systems. To solve these problems, in this article we propose a fast and low overhead metadata operation mechanism, called FLOMO. It first adopts a novel slotted-paging structure in NVM to reorganize dentry for efficiently performing dentry operations, and utilizes the red–black tree in DRAM to accelerate dentry lookup and the search process of dentry deletion. Moreover, FLOMO presents a selective journaling scheme for metadata updates, which partially logs the changes related to dentry in the proposed slotted page, thereby, mitigating the redundant journaling overhead. To verify FLOMO, we implement it in a typical NVM-based file system, the persistent memory file system (PMFS). Experimental results show that FLOMO accelerates the metadata operations in PMFS by 34.4% $\sim 59$ %, and notably reduces the journaling overhead for metadata, shortening the latency by 59% on average. For real-world applications, FLOMO has higher throughput compared with PMFS, PMFS without journal, and NOVA, achieving up to $2.1\times $ , $1.1\times $ , and $1.3\times $ performance improvement, respectively. [ABSTRACT FROM AUTHOR]

Secure deletion in flash-based storage is crucial for data security. However, existing secure deletion schemes for flash memory suffer from performance degradation and reliability issues and cannot provide secure deletion guarantees. Although emerging nonvolatile memory (NVM) allows in-place updates and provides high performance, it is unable to fully replace flash memory and, thus, cannot solve the secure deletion problem. In this article, we propose NVM-assisted secure deletion scheme for flash memory (NASA), a stale-free storage system that combines NVM and flash memory to provide immediate secure deletion without significant performance degradation in SSDs. NASA uses block erasure to provide secure deletion guarantees for flash memory and exploits NVM to conceal time-consuming erasure operations. We demonstrate that unless the unique characteristics of NVM are considered, schemes that merely implement existing approaches to secure deletion will end up with stale data replicas within their storage media. Moreover, we evaluate NASA with different real-world workloads and demonstrate that NASA increases the average latency by 0.01% compared to LRU and decreases 2.1% average latency over the FIFO caching policy. NASA is a novel storage system that provides strong secure deletion guarantees with high performance. [ABSTRACT FROM AUTHOR]

Nonvolatile memory (NVM) technologies, such as spin-transfer torque magnetic random access memory (STT-MRAM) and spin-orbit torque magnetic random access memory (SOT-MRAM), have significant advantages compared to conventional SRAM due to their nonvolatility, higher cell density, and scalability features. While previous work has investigated several architectural implications of NVM for generic applications, in this work, we present DeepNVM ++, a framework to characterize, model, and analyze NVM-based caches in GPU architectures for deep learning (DL) applications by combining technology-specific circuit-level models and the actual memory behavior of various DL workloads. We present both iso-capacity and iso-area performance and energy analysis for systems whose last-level caches rely on conventional SRAM and emerging STT-MRAM and SOT-MRAM technologies. In the iso-capacity case, STT-MRAM and SOT-MRAM provide up to $3.8 \times $ and $4.7 \times $ energy-delay product (EDP) reduction and $2.4 \times $ and $2.8 \times $ area reduction compared to conventional SRAM, respectively. Under iso-area assumptions, STT-MRAM and SOT-MRAM provide up to $2 \times $ and $2.3 \times $ EDP reduction and accommodate $2.3 \times $ and $3.3 \times $ cache capacity when compared to SRAM, respectively. We also perform a scalability analysis and show that STT-MRAM and SOT-MRAM achieve orders of magnitude EDP reduction when compared to SRAM for large cache capacities. Our comprehensive cross-layer framework is demonstrated on STT-/SOT-MRAM technologies and can be used for the characterization, modeling, and analysis of any NVM technology for last-level caches in GPUs for DL applications. [ABSTRACT FROM AUTHOR]

Neuromorphic computing chips consisting of crossbar arrays of emergent nonvolatile memory (NVM) have the potential of achieving both high energy efficiency and throughput as the low-power implementation of convolutional neural network (CNN) inference engines. However, such hardware has design constraints, such as its limited fan-in/fan-out and resource-inefficient mapping, that make the design and deployment of CNN on them challenging. As a result, the user has to design the CNN model with intricate knowledge of the hardware architecture and even cannot fit the models in the hardware for CNN with high resolution image input. In this article, we propose the use of aggregated subnets, NC-net, which is a constrained form of the traditional layer structure, to solve these issues. With our method, we put forward an energy-efficient buffer- and analogue-to-digital converter and digital-to-analogue converter (ADC/DAC)-free architecture and a scalable end-to-end solution that automatically satisfies the hardware constraints of crossbar architectures, while optimizing the resource usage. In our solution, the exploration and deployment of a CNN for a neuromorphic crossbar hardware start with a design front end based on TensorFlow. Our automated design flow maps the NC-net network from TensorFlow to the crossbar architecture. We tested our designs on both a simulator and a field-programmable gate array (FPGA) emulator with various benchmarks. In addition to general benchmarks, including MNIST, SVHN, CIFAR-10, and CIFAR-100, we tested our system on a real-world application, human detection with high resolution (224 $\times $ 224) images as the input. Our system achieves the state-of-the-art accuracy for these benchmarks on the crossbar-based neuromorphic hardware, with an accuracy of more than 90% for the latter. It also yielded up to $4.25\times $ improvement in the efficiency of spiking core usage compared to TrueNorth. [ABSTRACT FROM AUTHOR]

Emerging nonvolatile memories (NVMs) are considered as potential replacements of the traditional DRAM-based main memories. However, the nonvolatility feature of the NVMs may lead to the stealing of sensitive data stored in NVMs due to their prolonged data retention. Memory encryption turns out to be a viable option to provide data security. However, the existing encryption techniques, on account of the diffusion property, increase the number of bit-flips in the NVM cells, thus leading to their early wear out. Therefore, security and lifetime issues of the NVMs are difficult to go hand in hand. In this article, we identify words that are repeated in several memory blocks and term them as popular words. The proposal is to avoid the encryption of the popular words by maintaining them in a reference table. In our proposal, Pop-Crypt, every block to be written to the memory gets partially encrypted in which the popular words are replaced with pointers to the reference table, and other words get encrypted. The partially encrypted blocks (PEBs) reduce the number of bit-flips in PCM, thereby improving its lifetime significantly. Experimental results show that Pop-Crypt considerably improves lifetime, energy consumption, and system performance over baseline and a state-of-the-art technique. [ABSTRACT FROM AUTHOR]

Nonvolatile memories (NVMs) have been widely studied in the post-Moore era. However, noise/defect in NVMs has brought a challenging reliability problem in write/read access operations. A linear error correction code (ECC) has been widely used in memories to correct errors. In general, a codec hardware is required to encode or decode the information, resulting in area and energy overhead. In this article, we propose a new approach to implement the ECC codec by exploiting the existing write and read peripheral circuitry of NVMs based on an in-memory computing (IMC) architecture. In our approach, the desired code words can be generated through using write-like logic operations, given the original information and generation matrix during the encoding (write) process, while syndrome vectors (or error correction) can also be achieved through using read-like logic operations, given the parity-check matrix during the decoding (read) process, respectively. Therefore, we do not need a specific codec hardware but exploit the write-like and read-like logic operations. With an emerging toggle spin torque magnetic random access memory (TST-MRAM) and Hamming code as an example, we validated the feasibility of our approach and evaluated the performance of the design in the 40-nm technology node. The results show that our approach can significantly reduce energy consumption compared with state-of-the-art designs. [ABSTRACT FROM AUTHOR]

With the increasing demand of massive/big data applications, nonvolatile memory (NVM), such as phase-change memory (PCM), has become a promising candidate to replace DRAM because of its low leakage power, nonvolatility, and high density. However, most of the existing memory read/write intensive algorithms and data structures are not aware of the PCM write heterogeneity in terms of both energy consumption and latency. In particular, self-balancing binary search trees, which are widely used to manage massive data in the big-data era, were designed without the consideration of PCM characteristics. Thus, the multiple rotations of the tree balancing process would degrade the memory performance. This work explores the relations among nodes and analyzes tree operations, and the node indexing and address mapping are redesigned to reduce the tree management overhead on single-level cell (SLC) PCM by decreasing the number of bit flips of tree rotations. When multilevel cell (MLC) PCM is included, our address mapping algorithm is developed to reduce the total energy consumption and latency with considerations of the heterogeneous write operations of different cell states. Experimental results show that our solution significantly outperforms the original implementation of a self-balancing binary search tree when the amount of data is large. [ABSTRACT FROM AUTHOR]

Spin-transfer torque (STT) magnetic random access memory (MRAM) is gaining commercial traction in low-density embedded and standalone memories, but the available market opportunities would grow exponentially if STT-MRAM could approach dynamic random access memory (DRAM) bit density. Of course, achieving DRAM density will require, among other things, demonstrating the ability to pattern MRAM bits at an extremely tight pitch. Here, an experimental demonstration of fabrication and electrical testing of a STT-MRAM bit array are reported. By optimizing the hard mask and ion beam etching (IBE) processes, MRAM bit arrays with a full pitch down to 50 nm are fabricated, in which the bits are individually tested using a novel bottom-point-contact method. [ABSTRACT FROM AUTHOR]

In this work, we developed a model for a nonvolatile memory cell based on the electrical model for a TiOX/HfOx ReRAM cell and the hybrid electrothermal model of a VO2 Mott selector developed recently by our team. Both models have been calibrated and validated with experimental data, and the operating characteristics of a one-selector-one-ReRAM (1S1R) memory cell has been studied. The length of the selector layer was varied as a design parameter to meet the design requirements for proper read, write, and erase operations. Simulation results suggest that the modified selector cell with 60 nm length of the VO2 layer meets all the requirements for proper operation, with a cell write voltage of 1.6 V and erase voltage of 2.5 V. The access time for this structure was studied by benchmarking with experimental data. Write access time of 10.5 ns and erase access time of 16 ns have been obtained from simulations. [ABSTRACT FROM AUTHOR]

In this article, we characterized the charge trapping and detrapping behaviors of charge-trap transistors (CTTs) in standard 28-nm CMOS technology and formulated its programmable threshold voltage ( $V_{\mathrm {TH}}$ ). Both thin-oxide and thick-oxide CTT devices are measured, modeled, and analyzed. More than 50- and 100-mV continuous $V_{\mathrm {TH}}$ tuning ranges are achieved for thin and thick oxide devices, respectively. Multiple cycles of programming and erasing operations are demonstrated; however, the reliability needs to be solved in the future. To utilize the developed programmable threshold model, a nonvolatile memory (NVM) cell and an analog arithmetic unit (AAU) are proposed and simulated as two proof-of-concept CTT-based designs.

We perform a simulation-based analysis on the potential of emerging ferroelectric tunnel junctions (FTJs) as a memory device for crossbar arrays. Though FTJs are promising due to their low power switching characteristics compared to other emerging technologies, the greatest challenge for FTJs is the tradeoff between integration density and read performance. Our analysis highlights the need to co-optimize the ferroelectric thickness of the FTJ and read/write voltages to achieve proper functionality at large array sizes. Our analysis shows that FTJ-based crossbar achieves 93% higher sense margin at isoread power of 116 nW (per bit), but this FTJ design comes at a cost of $9.28\times $ higher write power at isowrite time of 250 ns. In response, we study the potential tradeoffs of design points outside the feasible region to understand what device characteristics are desired to overcome such challenges.

Endurance to cyclic program/erase (P/E) in a gate-all-around (GAA)-based SONOS flash memory device is improved by Joule heat, which was driven by gate-induced drain leakage (GIDL) current (${I}_{\text {GIDL}}$) with a current level of microamperes. By use of COMSOL simulation, induced temperature (${T}$) by the ${I}_{\text {GIDL}}$ is higher at the GAA with the ONO gate dielectrics than at a GAA with a thermal gate oxide due to the confined heat inside a silicon nanowire channel wrapped by a relatively thick ONO. Furthermore, ${T}$ is high enough to cure the damage from the iterative P/E operations. For a quantitative evaluation of the damage level before and after cyclic P/E, border trap density (${N}_{\text {bt}}$) in a tunneling oxide was analyzed with the aid of low-frequency noise (LFN) measurements. The damage was almost fully cured by ${I}_{\text {GIDL}}$ without an external Joule heater or structural modifications because it is always around a MOSFET. [ABSTRACT FROM AUTHOR]

Hf0.5Zr0.5O2 (HZO) ferroelectric random access memory (FeRAM) has been demonstrated in 130 nm node with 1T1C structure. To scale FeRAM to 28 nm or beyond, a high aspect ratio embedded dynamic random-access memory (eDRAM)-like 3-D cylinder capacitor is expected to ensure sufficient cell capacitance and sense margin. In this work, we investigate an alternative approach with 2T1C structure that takes advantage of a back-end-of-line (BEOL) oxide channel writing transistor, a small planar ferroelectric (FE) capacitor, and a silicon logic reading transistor. First, the proof-of-concept of 2T1C bit cell was experimentally demonstrated. Then, the scalability toward 28 nm or beyond was simulated with array-level parasitics. Thanks to the transconductance reading out mechanism, a 900 nm2 FE capacitor in 2T1C could significantly reduce energy consumption 6.4– $9.6\times $ compared to the traditional 1T1C FeRAM with similar cell area at 28 nm. Moreover, the area ratio between the FE capacitor and the read transistor is investigated both experimentally and with SPICE simulation, where adjustment of the pulsing scheme is needed for the maximum sense margin to occur. Finally, the performance at 7 nm is estimated in terms of read/write energy and cell area. [ABSTRACT FROM AUTHOR]

In this study, we present programming speed enhancement in amorphous oxide semiconductor memory thin-film transistor (TFT). We developed a nonvolatile memory transistor based on InZnSnO back-channel-etch TFT with InGaZnO charge storage layer inserted between gate insulators. We proposed double-gate (DG) and body-contacted (BC) memory structure to improve memory erase speed, which is the most important issue in oxide memory TFTs. DG memory did not show sufficient improvement due to large voltage drop in second gate insulator. BC memory, which can control back-channel potential directly, showed significant improvement on memory program/erase speed. [ABSTRACT FROM AUTHOR]

A new charge-trapping nonvolatile memory (NVM) with a fully same structure to thin-film transistor (TFT) is investigated. Different from the conventional NVM with block layer/charge-trapping layer/tunneling layer stack for charge storage, this NVM uses the metal-hydroxyl (M-OH) defect at the back channel for charge storage, which forms by the reaction of IGZO with moisture and acts as acceptor-like deep-level traps. Devices with various M-OH contents are prepared by changing thermal treatment. The device with high M-OH content displays good NVM performance in terms of its large memory window (1.5 V at ±10 V, 1s), high program/erase speeds (1.1 V at 10 V, 1 ms) and good data retention (78.9% retention after 10 years); for comparison, the device with low M-OH content exhibits good TFT characteristics in terms of its small sub-threshold swing (226 mV/dec), high carrier mobility (8.1 cm2/V.s) and good electrical stability (memory window ~ 0.2 V at ±10 V, 1s). Since the NVM and TFT have the same structure, both the devices can be simultaneously prepared combined with an extra treatment to modulate the M-OH content at the back channel, thus contributing to system-on-panel development. [ABSTRACT FROM AUTHOR]

We introduce “aCortex,” an extremely energy-efficient, fast, compact, and versatile neuromorphic processor architecture suitable for the acceleration of a wide range of neural network inference models. The most important feature of our processor is a configurable mixed-signal computing array of vector-by-matrix multiplier (VMM) blocks utilizing embedded nonvolatile memory arrays for storing weight matrices. Analog peripheral circuitry for data conversion and high-voltage programming are shared among a large array of VMM blocks to facilitate compact and energy-efficient analog-domain VMM operation of different types of neural network layers. Other unique features of aCortex include configurable chain of buffers and data buses, simple and efficient instruction set architecture and its corresponding multiagent controller, programmable quantization range, and a customized refresh-free embedded dynamic random access memory. The energy-optimal aCortex with 4-bit analog computing precision was designed in a 55-nm process with embedded NOR flash memory. Its physical performance was evaluated using experimental data from testing individual circuit elements and physical layout of key components for several common benchmarks, namely, Inception-v1 and ResNet-152, two state-of-the-art deep feedforward networks for image classification, and GNTM, Google's deep recurrent network for language translation. The system-level simulation results for these benchmarks show the energy efficiency of 97, 106, and 336 TOp/J, respectively, combined with up to 15 TOp/s computing throughput and 0.27-MB/mm2 storage efficiency. Such estimated performance results compare favorably with those of previously reported mixed-signal accelerators based on much less mature aggressively scaled resistive switching memories.

Conventional processors suffer from high access latency and power dissipation due to the demand for memory bandwidth for data-intensive workloads, such as machine learning and analytic. In-memory computing support for various memory technologies has provided formidable improvement in performance and energy for such workloads, alleviating the repeated accesses and data movement between CPU and storage. While many processing in-memory (PIM) works have been proposed to efficiently compute dot products using Kirchoff’s law, such solutions are unsuitable for many analytic workloads where working data is too large and too sparse to efficiently store in memory. This article closely focuses on the peripheral circuit design for diode-selected crossbars and configures the compute-embedded fabric to efficiently compute sparse matrix-vector multiplication (SpMV). On average, our proposed end-to-end SpMV accelerator achieves $7.7\times $ speed up and $4.9\times $ energy-savings compared to the state-of-the-art Fulcrum. [ABSTRACT FROM AUTHOR]

A tristate-nanoelectromechanical-switch-based ternary content-addressable memory (NEMTCAM) is proposed for the first time. In the proposed unit NEMTCAM cell, a single nanoelectromechanical (NEM) memory switch replaces two static random access memory cells. Due to the monolithic 3-D (M3D) integration and nonvolatile property of NEM memory switches, the proposed NEMTCAM achieves an 86.3% smaller area, 75.0% lower dynamic power consumption, and a 76.6% higher search speed than conventional ternary content-addressable memory (TCAM) in addition to a negligible static leakage current. [ABSTRACT FROM AUTHOR]

Hafnium oxide acts as a functional dielectric in a variety of traditional and emerging nonvolatile memory technologies. To investigate the effect of heavy ion irradiation on its crystalline structure, highly textured hafnium oxide films were irradiated with 1.635 GeV Au ions of fluences ranging from $1\times 10^{9}$ to $7\times 10^{12}$ ions/cm2. For monoclinic hafnium oxide films, a fluence-dependent defect-induced phase transition to a defect-stabilized tetragonal phase is identified. In low-temperature tetragonal hafnium oxide films, the X-ray diffraction (XRD) patterns show an out-of-plane lattice constant decrease with increasing irradiation fluence. Observed crystalline changes are strikingly similar to trends found for oxygen-engineered hafnium oxide films, directly grown at varying oxidation conditions. The correlation of structural changes with in vacuo electron spectroscopy data of oxygen-engineered films suggests that the irradiation of hafnium oxide leads to an oxygen loss that increases with fluence. Therefore, the underlying mechanism of the monoclinic to tetragonal phase transition is obviously directly related to oxygen defects. This new information allows predictions of device stability under swift heavy ion irradiation of hafnium oxide-based devices. [ABSTRACT FROM AUTHOR]

Emerging high-performance storage technologies are opening up the possibility of designing new distributed data acquisition (DAQ) system architectures, in which the live acquisition of data and their processing are decoupled through a storage element. An example of these technologies is 3D XPoint, which promises to fill the gap between memory and traditional storage and offers unprecedented high throughput for nonvolatile data. In this article, we characterize the performance of persistent memory devices that use the 3D XPoint technology, in the context of the DAQ system for one large Particle Physics experiment, DUNE. This experiment must be capable of storing, upon a specific signal, incoming data for up to 100 s, with a throughput of 1.5 TB/s, for an aggregate size of 150 TB. The modular nature of the apparatus allows splitting the problem into 150 identical units operating in parallel, each at 10 GB/s. The target is to be able to dedicate a single CPU to each of those units for DAQ and storage. [ABSTRACT FROM AUTHOR]

Emerging nonvolatile memories (NVMs), such as resistive RAM (RRAM) and spin-transfer-torque RAM (STTRAM), present exciting opportunities for data storage applications and offer improved access speeds, retention times, power consumption, and scalability. However, these technologies leak the Hamming weight of data through power side-channel during read and write operations. We propose a technique leveraging on-chip capacitor and voltage regulator (VR) that powers the NVM read/write operations. The side-channel leakage is eliminated due to the isolation of memory array from the external power supply during read/write operations. The residual charge on capacitor bank is discarded safely to prevent information leakage during capacitor recharging. The VR ensures a steady voltage during the entire read/write operations even though the capacitor discharges. The design presents a performance (instructions per cycle) degradation of 0.53%–1.2% under parsec and splash-2 benchmarks and incurs an area overhead of $\sim 3.54\times 10^{-5}$ % and an energy overhead of $\sim 3.05 \times 10^{-5}$ % for a 4-Mb RRAM memory array. For a 64-bit word, the design improves security by 2.7 $\times \,\,10^{19} \times $ to $2^{64} \times $. SecNVM should be used in small security-critical memory macros to limit the overhead. SecNVM is generic and could protect any security module such as encryption engines, against power side-channel attacks. [ABSTRACT FROM AUTHOR]

We report a heterojunction, nonvolatile memory (NVM) device with amorphous indium-gallium-zinc oxide (a – IGZO) and low-temperature polysilicon (LTPS) stack. The LTPS layer was achieved by blue laser annealing of amorphous silicon. The a – IGZO/LTPS heterojunction NVM exhibits a large threshold voltage $(\Delta {\mathsf {V}}_{\mathsf {Th}}({\mathsf {V}}))$ memory window of 19.2 V with prolonged operational stability. An increase in channel length (L) (from 2 to $20~\mu \text{m}$) exhibits a stable memory window. The neutral oxygen vacancy states in a – IGZO trap the carriers at a – IGZO/LTPS interface and then transforms into a metastable state, (${\mathsf {D}}^{\mathsf {O}}+ {\mathsf {h}}^{+}(2 {\mathsf {h}}^{+})\to {\mathsf {D}}^{+}/ {\mathsf {D}}^{++}$ or ${\mathsf {D}}^{\mathsf {O}}+ {\mathsf {e}}^{-}(2 {\mathsf {e}}^{-})\to {\mathsf {D}}^{-}/ {\mathsf {D}}^{--}$), which is the key to the operation of a – IGZO/LTPS heterojunction NVM. [ABSTRACT FROM AUTHOR]

A low-voltage programmable gate-all-around (GAA) nanosheet poly-Si thin-film transistor (TFT) nonvolatile memory (NVM), which uses band-to-band tunneling induced hot electron (BBHE) programming, is demonstrated. The BBHE method is extremely efficient for programming data in the p-type GAA nanosheet TFT NVM because the GAA nanosheet structure enhances the source-to-drain component of the electric field in its channel. Therefore, the enhanced electric field of the BBHE phenomenon creates energetic electrons that surmount the tunneling oxide barrier easily and pass shallow traps in the charge trapping layer of the GAA TFT NVM. Consequently, the p-type GAA TFT NVM achieves low-voltage programming bias and satisfactory data retention

Resistive random-access memory (RRAM) with atomic layer deposited (ALD) nitrogen-doped aluminum oxide (AlOxNy) resistive dielectric appropriate for high-density 3-D vertical via array is demonstrated. With appropriate ALD electrodes, the RRAM exhibits almost forming-free, sub-microamperes programming currents, and appropriate resistance ranges. As the via size is scaled down, the set voltage and reset current decrease and the memory window widens, due to the 3-D nature of the device. Programming endurance of 5 × 104 cycles and retention up to 10 years at 90 °C are demonstrated. [ABSTRACT FROM AUTHOR]

We present a nonvolatile resistive-gate metal–oxide–semiconductor-field-effect transistor (RG-MOSFET). An RG-MOSFET comprises a MOSFET and dielectric layers sandwiched between the top and bottom electrode metal–dielectric–metal (MDM). The gate of the MOSFET is electrically connected to the bottom electrode of MDM in series. Dielectric layers of MDM are composed of a resistance-switching layer made by hafnium oxynitride (HfON) and a resistance-nonswitching layer by hafnium dioxide (HfO2). RG-MOSFET as a memory can be achieved by resistance changes in the HfON. Eight distinguishable resistance values can be programmed randomly, which is performed as a 3 bit per cell through the edge Fowler–Nordheim (FN) mechanism between the top electrode metal and the drain of RG-MOSFET. The external voltage applied to the top electrode is divided by the MDM and the gate dielectric, and the threshold voltage (Vth) of an RG-MOSFET is modulated by different resistance values of MDM. Therefore, states stored in MDM can be read out from the drain-current level of an RG-MOSFET. FORMing-free characteristic of MDM is required for bipolar operation. A ratio of drain current between the high-resistance state (HRS) and the low-resistance state (LRS) is 105. Gradual SET/RESET is executed to tune the drain current by pulse operations; 105 endurance cycles of RG-MOSFETs are demonstrated, and a retention test can be passed for more than 5 × 106 (35 days) at 125 °C. [ABSTRACT FROM AUTHOR]

Emerging nonvolatile memories (eNVMs) have demonstrated satisfactory accuracy on various applications in deep learning. Characterized by high density and low leakage power consumption, resistive random access memory (RRAM) becomes very attractive in synaptic devices for deep neural networks (DNNs). RRAM-based synaptic devices include both analog and discrete versions. Unlike analog RRAM synapses which suffer from nonlinearity, discrete but multistate RRAM synapses are better suited for neural network hardware implementation. In this article, the multistate operation in RRAM arrays has been proposed as a synaptic device for DNN inference. Four-state conductance has been achieved in HfOx-based RRAM synaptic arrays. The impact of total ionizing dose (TID) on the multistate behavior of HfOx-based RRAM is investigated by irradiating a one-transistor–one-resistor (1T1R) 64-kb array with CMOS peripheral decoding circuitry fabricated at the 90-nm technology node with Co-60 gamma rays (60Co $\gamma $ -ray irradiation). [ABSTRACT FROM AUTHOR]

This article investigates the impact of interface trapped-charge variations on the dimensional scaling of the ferroelectric field-effect transistor (FeFET) nonvolatile memory (NVM) under two scenarios: a uniform ferroelectric and random ferroelectric-dielectric (FE-DE) phase distribution. Our study indicates that both memory window (MW) and read margin decrease with increasing trap density (< nT >), and the MW of FeFET devices with scaled channel width can be more vulnerable to the trapped-charge variations than that with scaled gate length. Under the presence of the FE-DE phase variation, for low < nT >, the impact of trapped charges is mainly on the MW degradation for the high MW instances. As the < nT > continues to rise, the trapped charges can further worsen the worst case MW significantly. Besides, when down-scaling the interfacial layer thickness of the FeFET device to increase the MW, the increased σ MW due to the random interface trapped charges may also need to be considered. Our study may provide insights for device design with advanced FeFET NVMs. [ABSTRACT FROM AUTHOR]

This brief investigates scaled 2-D MoS2 ferroelectric field-effect transistor (FeFET) nonvolatile memories (NVMs) considering the trapped-charge-induced variability with the aid of Technology Computer Aided Design (TCAD) atomistic simulations. Our study indicates that, compared with the Si channel, the monolayer MoS2 channel with larger electron affinity and bandgap energy can result in an FeFET NVM with larger memory window (MW). Moreover, due to its lower channel permittivity and channel thickness, the 2-D MoS2 FeFET possesses a superior immunity to trapped-charge-induced variability, and the gap in MW between MoS2 and Si FeFETs enlarges under the presence of trapped charges. Besides, due to its atomically thin channel thickness and superior electrostatic integrity, the scaled 2-D MoS2 FeFET possesses a remarkably better read margin than the Si counterpart. Our study may provide insights for future scaling of FeFET NVMs. [ABSTRACT FROM AUTHOR]

A low-cost fabrication process of Hf1-xZrxO2 (HZO) nonvolatile memory (NVM) was proposed and its characteristics were investigated. We successfully fabricated a ferroelectric tunnel junction (FTJ) device with tunable conductance for neural network applications. The proposed FTJ device exhibits excellent performances, such as large conductance ratio of ~40 for a 500-ns pulse and thus satisfied low-power consumption of write pulse (1 fJ per bit) and fast write speed (<500 ns) requirements. Furthermore, we revealed that the metal–ferroelectric–insulator–semiconductor structure had a higher tunneling electroresistance ratio than the metal–ferroelectric–insulator–metal structure. Moreover, the polarization operation of our FTJ devices achieved low-power analog-like conductance transition, multilevel operation, and even endurance characteristics is promising. These results demonstrate that the FTJ has high potential to be an ideal emerging memory for neuromorphic computing. Therefore, HZO-based devices are promising materials in neural network applications for next-generation devices. [ABSTRACT FROM AUTHOR]

Since static random access memory (SRAM)-based field-programmable gate array (FPGA) has limited density and comparatively high leakage power, researchers have proposed FPGA architectures based on emerging nonvolatile memories (NVMs) to satisfy the requirements of data-intensive and low-power applications. Among all components, block random access memory (BRAM) has the severest endurance problem in FPGA. Unluckily, traditional wear leveling (TWL) strategies cannot be directly applied to nonvolatile FPGA because it may induce large performance overhead. In this article, we propose performance-aware wear leveling schemes for nonvolatile FPGA to improve its lifetime. Two strategies pertaining to coarse-grained wear leveling (C-Pearl) and fine-grained wear leveling (F-Pearl) are developed to balance inter-BRAM and intra-BRAM writes. Procedures, including static analysis, wear leveling-guided placement, and reconfiguration are discussed. A supportive circuit design is proposed, too. The evaluation shows that C-Pearl and F-Pearl can achieve 34% and 46% higher lifetime improvement and simultaneously 8% and 11% lower performance overhead than TWL. [ABSTRACT FROM AUTHOR]

Single ferroelectric-FET (FeFET) reconfigurable logic-in-memory is an attractive beyond-von-Neumann scheme for data-centric computing. Different from using body-to-source voltage to tune the operating point of the FeFET for reconfigurability, this brief presents an alternative approach based on the unique ferroelectric minor-loop behavior (which results from the partial switching of domains). Through simulation, we show that the NAND/ NOR reconfigurability can theoretically be achieved by adequately modulating the reference and writing pulses for the FeFET nonvolatile memory (NVM). Our approach may serve as an option when the body-effect capability is lacking for nonplanar FeFETs or 3-D stacked FeFETs which can be crucial to future high-density integration. [ABSTRACT FROM AUTHOR]

Current DRAM-based memory systems face the scalability challenges in terms of memory density, energy consumption, and monetary cost. Hybrid memory architectures composed of emerging nonvolatile memory (NVM) and DRAM is a promising approach to large-capacity and energy-efficient main memory. However, hybrid memory systems pose a new challenge to on-chip cache management due to the asymmetrical penalty of memory access to DRAM and NVM in case of cache misses. Cache hit rate is no longer an effective metric for evaluating memory access performance in hybrid memory systems. Current cache replacement policies that aim to improve the cache hit rate are not efficient either. In this article, we take into account the asymmetry of the cache miss penalty on DRAM and NVM, and advocate a more general metric, average memory access time (AMAT), to evaluate the performance of hybrid memories. We propose a miss penalty aware LRU-based cache replacement policy (MALRU) for hybrid memory systems. MALRU is aware of the source (DRAM or NVM) of missing blocks and preserves high-latency NVM blocks as well as low-latency DRAM blocks with good temporal locality in the last level cache. The experimental results show that MALRU can improve system performance by up to 22.8% and 13.1%, compared to LRU and the state-of-the-art hybrid memory aware cache partitioning technique policy, respectively. [ABSTRACT FROM AUTHOR]

Nonvolatile memory (NVM)-based computing in-memory (CIM) is a promising solution to data-intensive applications. This work proposes a 2T2R resistive random access memory (ReRAM) architecture that supports three types of CIM operations: 1) ternary content addressable memory (TCAM); 2) logic in-memory (LiM) primitives and arithmetic blocks such as full adder (FA) and full subtractor; and 3) in-memory dot-product for neural networks. The proposed architecture allows the NVM operations in both 2T2R and conventional 1T1R configurations. The proposed LiM full adder (LiM-FA) improves the delay, the static power, and the dynamic power by $3.2\times $ , $1.2\times $ , and $1.6\times $ , respectively, compared with state-of-the-art LiM-FAs. Furthermore, based on different optimization techniques and robustness analysis, a lower precharge voltage is set for each mode. This reduces the TCAM search energy and 1T1R ReRAM access energy by $1.6\times $ and $1.14\times $ , respectively, compared with the case without optimizations. [ABSTRACT FROM AUTHOR]

In this era of nanoscale technologies, the inherent characteristics of some nonvolatile devices, such as resistive random access memory (ReRAM), phase-change material (PCM), and spintronics, can emulate stochastic functionalities. Traditionally, these devices have been engineered to suppress the stochastic switching behavior as it poses reliability concerns for memory storage and logic applications. However, leveraging stochasticity in such devices led to a renewed interest in hardware–software codesign of stochastic algorithms since the CMOS-based implementations of stochastic algorithms involve cumbersome circuitry to generate “stochastic bits.” In this article, we consider two classes of problems: deep neural networks (DNNs) and combinatorial optimization. The rapidly growing demands of artificial intelligence (AI) have sparked an interest in energy-efficient implementations of large DNNs, with binary representations of synaptic weights and neuronal activities. Stochasticity plays an important role in leveraging the benefits of these binary representations, leading to model compression and optimization during training. In combinatorial optimization, such as graph coloring or traveling salesman problems, stochastic algorithms, such as the Ising computing model, have been shown to be effective. These problems require exhaustive computational procedures, and the Ising model uses a natural annealing agent to achieve near-optimal solutions in a reasonable timescale, without getting stuck in “local minima.” In this article, we present a broad review of stochastic computing utilizing the stochastic switching characteristics of devices based on nanoscale nonvolatile technologies. We show how to codesign of the devices and algorithms that can enable optimal solutions for both combinatorial problems and binary neural networks for local learning and inference. Directly mapping the nonvolatile device characteristics to the stochastic algorithms without the need for storing the bits in a separate memory leads to efficient use of hardware. [ABSTRACT FROM AUTHOR]

The current mobile applications have rapidly growing memory footprints, posing a great challenge for memory system design. Insufficient DRAM main memory will incur frequent data swaps between memory and storage, a process that hurts performance, consumes energy, and deteriorates the write endurance of typical flash storage devices. Alternately, a larger DRAM has higher leakage power and drains the battery faster. Furthermore, DRAM scaling trends make further growth of DRAM in the mobile space prohibitive due to cost. Emerging nonvolatile memory (NVM) has the potential to alleviate these issues due to its higher capacity per cost than DRAM and minimal static power. Recently, a wide spectrum of NVM technologies, including phase-change memories (PCMs), memristor, and 3-D XPoint has emerged. Despite the mentioned advantages, NVM has longer access latency compared to DRAM and NVM writes can incur higher latencies and wear costs. Therefore, the integration of these new memory technologies in the memory hierarchy requires a fundamental rearchitecting of traditional system designs. In this work, we propose a hardware-accelerated memory manager (HMMU) that addresses in a flat address space, with a small partition of the DRAM reserved for subpage block-level management. We design a set of data placement and data migration policies within this memory manager such that we may exploit the advantages of each memory technology. By augmenting the system with this HMMU, we reduce the overall memory latency while also reducing writes to the NVM. The experimental results show that our design achieves a 39% reduction in energy consumption with only a 12% performance degradation versus an all-DRAM baseline that is likely untenable in the future. [ABSTRACT FROM AUTHOR]

Deep neural network (DNN) hardware designs have been bottlenecked by conventional memories, such as SRAM due to density, leakage, and parallel computing challenges. Resistive devices can address the density and volatility issues but have been limited by peripheral circuit integration. In this work, we present a resistive RAM (RRAM)-based in-memory computing (IMC) design, which is fabricated in 90-nm CMOS with monolithic integration of RRAM devices. We integrated a 128 × 64 RRAM array with CMOS peripheral circuits, including row/column decoders and flash analog-to-digital converters (ADCs), which collectively become a core component for scalable RRAM-based IMC for large DNNs. To maximize IMC parallelism, we assert all 128 wordlines of the RRAM array simultaneously, perform analog computing along the bitlines, and digitize the bitline voltages using ADCs. The resistance distribution of low-resistance states is tightened by an iterative write-verify scheme. Prototype chip measurements demonstrate high binary DNN accuracy of 98.5% for MNIST and 83.5% for CIFAR-10 data sets, with 24 TOPS/W and 158 GOPS. This represents 22.3 × and 0.1 × improvements in throughput and energy–delay product (EDP), respectively, compared with the state-of-the-art literature, which can enable intelligent functionalities for area-/energy-constrained edge computing devices. [ABSTRACT FROM AUTHOR]

Journaling techniques play an important role in addressing the reliability issue of filesystems caused by the volatile dynamic random access memory (DRAM)-based buffer cache. However, journaling techniques introduce a large number of extra storage writes, which greatly degrades system performance, especially for mobile devices. Emerging nonvolatile memory (NVM) technologies bring a new perspective of solving the write amplification issue caused by journaling. By adopting NVM as the buffer cache, the committed data can be maintained in NVM before being written back to the storage, thus, eliminating the journaling overhead. However, simply utilizing NVM as the buffer cache suffers from the limited lifetime and the relatively longer write latency of NVM. In this paper, we present a hybrid buffer cache architecture, named UniBuffer, by combing NVM with dynamic random access memory (DRAM) to reduce the journaling overhead and overcome the inherent constraints of NVM. In UniBuffer, we first propose a journaling-aware page management (JAPM) policy to smartly allocate data to DRAM and NVM pages. JAPM puts infrequently updated data in NVM to reduce the journaling overhead and frequently updated data in DRAM to improve the write performance and lifetime of the hybrid buffer cache. In addition, since data in one journaling transaction may be dispersed in NVM and DRAM simultaneously, different committing policies are required for different storage media, respectively. In order to guarantee the atomicity of the transaction execution in the hybrid cache architecture, a partial in-place commit (PIPC) journaling scheme is proposed to coordinate different committing patterns for NVM and DRAM. We have implemented the proposed techniques on Linux 3.14.52 and measured the performance with representative I/O-intensive benchmarks. The experimental results show that our scheme effectively improves the I/O performance compared with the ext4 filesystem and prolongs the lifetime of the hybrid buffer cache compared with the union of buffer cache and journaling (UBJ) scheme. [ABSTRACT FROM AUTHOR]

As cloud computing and big data applications become more popular, the demand for large capacity memory and data preservation in memory increases. Therefore, nonvolatile memory (NVM) with high capacity is being actively developed. A hybrid memory that comprises both NVM and DRAM and provides both high access speed and nonvolatility has become a major trend. However, compared to DRAM, NVM in the hybrid memory typically suffers from a shorter lifetime and higher latency. To improve the lifetime and address the latency issues associated with hybrid memory, we propose a global clean page first replacement (GCPF) to reduce the write operations to NVM. We also propose an index-aware multistream prefetcher (IAMSP) that considers the indexes of prefetch candidates individually so as to prefetch pages from NVM more accurately. Benchmarks with a large memory footprint are used to evaluate the proposed schemes. The experimental results show that GCPF enhances lifetime by 56.8% as compared to LRU, on average. When applying prefetching schemes on GCPF, the lifetime is insignificantly degraded. In addition, IAMSP reduces DRAM misses by 42.0% as compared to LRU, while a modern prefetcher that can change the prefetch degree dynamically only reduces DRAM misses by 38.0%, on average. When applying both GCPF and IAMSP, the average access latency can be reduced by 28.8% as compared to LRU. [ABSTRACT FROM AUTHOR]