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For neural recording applications, a low power neural signal acquisition amplifier has been proposed. Since extracellular neural signals are weak in amplitude and low in frequency, amplification of these signals with less noise and low power is a must for epilepsy prediction. The proposed amplifier employs anti parallel diode connected PMOS transistors as pseudo resistors to realize low frequency high pass function (LFHPF), Transconductance (gm - boosted) Low Noise Amplifier to achieve high gain and Gm-C LPF to select the desired band of neural signals. The proposed amplifier achieves a gain of 44.6 dB with 61.75% reduction in power consumption and 1 µV/ Hz less input referred noise compared to the conventional amplifier. These results have been authorized using the cadence spectre trainer with CMOS 180 nm. A greater part of driven based rectifier is used as MOSFET to supply adequate power, as this structure can be made fully implantable. Hence, the neural amplifier can be made compatible with a wireless programmable, implantable neural recording micro system. [ABSTRACT FROM AUTHOR]

Scaling down technology demotes the parameters of AC-coupled neural amplifiers, such as increasing the low-cutoff frequency due to the short-channel effects. To improve the low-cutoff frequency, one solution is to increase the feedback capacitors' value. This solution is not desirable, as the input capacitors have to be increased to maintain the same gain, which increases the area and decreases the input impedance of the neural amplifier. We analytically analyze the small-signal behavior of the neural amplifier and prove that the main reason for the increase of the low-cutoff frequency in advanced CMOS technologies is the reduction of the input resistance of the operational transconductance amplifier (OTA). We also show that the reduction of the input resistance of the OTA is due to the increase in the gate oxide leakage in the input transistors. In this paper, we explore this fact and propose two solutions to reduce the low-cutoff frequency without increasing the value of the feedback capacitor. The first solution is performed by only simulation and is called cross-coupled positive feedback that uses pseudoresistors to provide a negative resistance to increase the input resistance of the OTA. As an advantage, only standard CMOS transistors are used in this method. Simulation results show that a low-cutoff frequency of 1.5 Hz is achieved while the midband gain is 30.4 dB at 1 V. In addition, the power consumption is 0.6 μW. In the second method, we utilize thick-oxide MOS transistors in the input differential pair of the OTA. We designed and fabricated the second method in the 65 nm TSMC CMOS process. Measured results are obtained by in vitro recordings on slices of mouse brainstem. The measurement results show that the bandwidth is between 2 Hz and 5.6 kHz. The neural amplifier has 34.3 dB voltage gain in midband and consumes 3.63 μW at 1 V power supply. The measurement results show an input-referred noise of 6.1 μVrms and occupy 0.04 mm2 silicon area.

Scaling down technology demotes the parameters of AC-coupled neural amplifiers, such as increasing the low-cutoff frequency due to the short-channel effects. To improve the low-cutoff frequency, one solution is to increase the feedback capacitors' value. This solution is not desirable, as the input capacitors have to be increased to maintain the same gain, which increases the area and decreases the input impedance of the neural amplifier. We analytically analyze the small-signal behavior of the neural amplifier and prove that the main reason for the increase of the low-cutoff frequency in advanced CMOS technologies is the reduction of the input resistance of the operational transconductance amplifier (OTA). We also show that the reduction of the input resistance of the OTA is due to the increase in the gate oxide leakage in the input transistors. In this paper, we explore this fact and propose two solutions to reduce the low-cutoff frequency without increasing the value of the feedback capacitor. The first solution is performed by only simulation and is called cross-coupled positive feedback that uses pseudoresistors to provide a negative resistance to increase the input resistance of the OTA. As an advantage, only standard CMOS transistors are used in this method. Simulation results show that a low-cutoff frequency of 1.5 Hz is achieved while the midband gain is 30.4 dB at 1 V. In addition, the power consumption is 0.6 μW. In the second method, we utilize thick-oxide MOS transistors in the input differential pair of the OTA. We designed and fabricated the second method in the 65 nm TSMC CMOS process. Measured results are obtained by in vitro recordings on slices of mouse brainstem. The measurement results show that the bandwidth is between 2 Hz and 5.6 kHz. The neural amplifier has 34.3 dB voltage gain in midband and consumes 3.63 μ W at 1 V power supply. The measurement results show an input-referred noise of 6.1 μ V rms and occupy 0.04 mm 2 silicon area. [ABSTRACT FROM AUTHOR]

An ultralow power 0.6 V neural amplifier with on-chip analog spike detection is presented. A capacitively-coupled instrumentation amplifier (CCIA) with the current-reused and self-biased scheme is proposed to reduce the overall power consumption and to enhance the noise efficiency. The transistors in the amplifier are operated in the subthreshold region to enhance noise performance. The analog-domain spike detection based on a low power peak detector can reduce the overall power consumption. The circuit is fabricated using the standard 0.18 μm CMOS process. The passband of the circuit is from 6.4 Hz to 4.46 kHz. Input-referred noise is 10.68 μVrms. The supply voltage is 0.6 V, and the power consumption of the singlestage CCIA is 50.6 nW. The CCIA achieves a good noise efficiency factor and power efficiency factor of 1.79 and 1.93, respectively. The overall power consumption including two CCIAs, the programmable gain amplifier, and the analog spike detector is 269.8 nW. Input spikes with an amplitude of 50 μV at 100-Hz intervals are accurately detected.

This article demonstrates a scalable, time-division multiplexed biopotential recording front-end capable of real-time differential- and common-mode artifact suppression. A delta-encoded recording architecture exploits the power spectral density (PSD) characteristics of Electrocorticography (ECoG) recordings, combining an 8-bit ADC, and an 8-bit DAC to achieve 14 bits of dynamic range. The flexibility of the digital feedback architecture is leveraged to time-division multiplex 64 differential input channels onto a shared mixed-signal front-end, reducing channel area by 2x compared to the state-of-the-art. The feedback DAC used for delta-encoding also serves to cancel differential artifacts with an off-chip adaptive loop. Analysis of this architecture and measured silicon performance of a 65 nm CMOS test-chip implementation, both on the bench and in-vivo, are included with this paper. [ABSTRACT FROM AUTHOR]

This report presents characterizations of in vivo neural recordings performed with a CMOS multichannel neural recording chip that uses rapid multiplexing directly at the electrodes, without any pre-amplification or buffering. Neural recordings were taken from a 16-channel microwire array implanted in rodent cortex, with comparison to a gold-standard commercial bench-top recording system. We were able to record well-isolated threshold crossings from 10 multiplexed electrodes and typical local field potential waveforms from 16, with strong agreement with the standard system (average SNR = 2.59 and 3.07 respectively). For 10 electrodes, the circuit achieves an effective area per channel of 0.0077 mm2, which is >5x smaller than typical multichannel chips. Extensive characterizations of noise and signal quality are presented and compared to fundamental theory, as well as results from in vivo and in vitro experiments. By demonstrating the validation of rapid multiplexing directly at the electrodes, this report confirms it as a promising approach for reducing circuit area in massively-multichannel neural recording systems, which is crucial for scaling recording site density and achieving large-scale sensing of brain activity with high spatiotemporal resolution. [ABSTRACT FROM AUTHOR]

A subthreshold MOS-based pseudo-resistor featuring a very high value and ultra-low distortion is proposed. A bandpass neural amplifier with a very low high-pass cutoff frequency is designed, to demonstrate the linearity of the proposed resistor. A BJT less CTAT current generator has been introduced to minimize the temperature drift of the resistor and make tuning easier. The standalone resistor has achieved 0.5% better linearity and a 12% improved temperature coefficient over the existing architectures. A neural amplifier has been designed with the proposed resistor as a feedback element. It demonstrated 31 dB mid-band gain and a low-pass cutoff frequency of 0.85 Hz. The circuit operates from a 1 V supply and draws 950 nA current at room temperature. [ABSTRACT FROM AUTHOR]

There are neural recording applications in which the amplitude of common-mode interfering signals is several orders of magnitude higher than the amplitude of the signals of interest. This challenging situation for neural amplifiers occurs, among other applications, in neural recordings of weakly electric fish or nerve activity recordings made with cuff electrodes. This paper reports an integrated neural amplifier architecture targeting in-vivo recording of local field potentials and unitary signals from the brain stem of a weakly electric fish Gymnotus omarorum. The proposed architecture offers low noise, high common-mode rejection ratio (CMRR), current-efficiency, and a high-pass frequency fixed without MOS pseudoresistors. The main contributions of this work are the overall architecture coupled with an efficient and simple single-stage circuit for the amplifier main transconductor, and the ability of the amplifier to acquire biopotential signals from high-amplitude common-mode interference in an unshielded environment. A fully-integrated neural preamplifier, which performs well in line with the state-of-the-art of the field while providing enhanced CMRR performance, was fabricated in a 0.5  $\mu$ m CMOS process. Results from measurements show that the gain is 49.5 dB, the bandwidth ranges from 13 Hz to 9.8 kHz, the equivalent input noise is 1.88  $\mu$ V $_{\text{rms}}$ , the CMRR is 87 dB and the Noise Efficiency Factor is 2.1. In addition, in-vivo recordings of weakly electric fish neural activity performed by the proposed amplifier are introduced and favorably compared with those of a commercial laboratory instrumentation system. [ABSTRACT FROM AUTHOR]

This work presents a low-power biopotential amplifier integrated circuit (IC) for implantable neural recording prosthetic devices which have been implemented using 0.18-m CMOS technology. The proposed neural recording amplifier is based on a capacitive-feedback architecture and utilizes a low-power two-stage source-degenerated operational transconductance amplifier (OTA) with a modified current buffer compensation for large open-loop gain, low-noise and wide bandwidth. The designed amplifier achieves a measured gain of 39.2dB with a bandwidth between 0.25Hz to 28kHz, integrated input referred noise of 5.79Vrms and noise efficiency factor of 3.16. The IC consumes 2.4W at 1.2V supply and the die area is 0.09mm2. [ABSTRACT FROM AUTHOR]

The recently growing progress in neuroscience research and relevant achievements, as well as advancements in the fabrication process, have increased the demand for neural interfacing systems. Brain−machine interfaces (BMIs) have been revealed to be a promising method for the diagnosis and treatment of neurological disorders and the restoration of sensory and motor function. Neural recording implants, as a part of BMI, are capable of capturing brain signals, and amplifying, digitizing, and transferring them outside of the body with a transmitter. The main challenges of designing such implants are minimizing power consumption and the silicon area. In this paper, multi-channel neural recording implants are surveyed. After presenting various neural-signal features, we investigate main available neural recording circuit and system architectures. The fundamental blocks of available architectures, such as neural amplifiers, analog to digital converters (ADCs) and compression blocks, are explored. We cover the various topologies of neural amplifiers, provide a comparison, and probe their design challenges. To achieve a relatively high SNR at the output of the neural amplifier, noise reduction techniques are discussed. Also, to transfer neural signals outside of the body, they are digitized using data converters, then in most cases, the data compression is applied to mitigate power consumption. We present the various dedicated ADC structures, as well as an overview of main data compression methods.

When designing an analog front-end for neural interfacing, it is hard to evaluate the interplay of priority features that one must upkeep. Given the competing nature of design requirements for such systems a good understanding of these trade-offs is necessary. Low power, chip size, noise control, gain, temporal resolution and safety are the salient ones. There is a need to expose theses critical features for high performance neural amplifiers as the density and performance needs of these systems increases. This review revisits the basic science behind the engineering problem of extracting neural signal from living tissue. A summary of architectures and topologies is then presented and illustrated through a rich set of examples based on the literature. A survey of existing systems is presented for comparison based on prevailing performance metrics.

We present a high electrode density and high channel count CMOS (complementary metal-oxide-semiconductor) active neural probe containing 1344 neuron sized recording pixels (20 μm × 20 μm) and 12 reference pixels (20 μm × 80 μm), densely packed on a 50 μm thick, 100 μm wide, and 8 mm long shank. The active electrodes or pixels consist of dedicated in-situ circuits for signal source amplification, which are directly located under each electrode. The probe supports the simultaneous recording of all 1356 electrodes with sufficient signal to noise ratio for typical neuroscience applications. For enhanced performance, further noise reduction can be achieved while using half of the electrodes (678). Both of these numbers considerably surpass the state-of-the art active neural probes in both electrode count and number of recording channels. The measured input referred noise in the action potential band is 12.4 μVrms, while using 678 electrodes, with just 3 μW power dissipation per pixel and 45 μW per read-out channel (including data transmission). [ABSTRACT FROM AUTHOR]

In this paper, we present a low-power, low-noise fully differential pseudo-open-loop preamplifier with programmable bandwidth for monitoring neural activities. The proposed pseudo-open-loop topology can achieve high-power-noise efficiency as well as high linearity and precise gain control over process. The proposed fully differential preamplifier can balance the common mode of the differential outputs without a common-mode feedback circuit, and bias the ac-coupled input transistors without an external reference. A current-ratio gain design can set a stable gain over process and bias current variations. A programmable embedded gm-C low-pass filter (LPF) can be tuned by adjusting bias current, so that the proposed preamplifier can be configured to be used in recording single neuron spikes or field potentials (EEG, ECoG). The proposed amplifier is configured to consume 400 nA at 2.5-V power supply; the total chip area is 0.189 mm2. The measured thermal noise floor is 85 nV/ $\surd $ Hz and input-referred noise is 1.69~\mu \text{V}_{\mathrm {rms}} from 0.3 Hz to 1 kHz when using a chopper stabilization technique to suppress 1/f noise. The fabricated preamplifier shows a noise efficiency factor of 2.43 in the fully differential topology. [ABSTRACT FROM PUBLISHER]

In vivo recording of neural action-potential and local-field-potential signals requires the use of high-resolution penetrating probes. Several international initiatives to better understand the brain are driving technology efforts towards maximizing the number of recording sites while minimizing the neural probe dimensions. We designed and fabricated (0.13-$\mu$m SOI Al CMOS) a 384-channel configurable neural probe for large-scale in vivo recording of neural signals. Up to 966 selectable active electrodes were integrated along an implantable shank (70 \mu$m wide, 10 mm long, 20  \mu$m thick), achieving a crosstalk of dB. The probe base (5 \times$ 9 mm^2$ ) implements dual-band recording and a 171.6 Mbps digital interface. Measurement results show a total input-referred noise of 6.4 \mu and a total power consumption of 49.1 $\mu$W/channel. [ABSTRACT FROM PUBLISHER]

Neural recording systems that interface with implanted microelectrodes are used extensively in experimental neuroscience and neural engineering research. Interface electronics that are needed to amplify, filter, and digitize signals from multichannel electrode arrays are a critical bottleneck to scaling such systems. This paper presents the design and testing of an electronic architecture for intracortical neural recording that drastically reduces the size per channel by rapidly multiplexing many electrodes to a single circuit. The architecture utilizes mixed-signal feedback to cancel electrode offsets, windowed integration sampling to reduce aliased high-frequency noise, and a successive approximation analog-to-digital converter with small capacitance and asynchronous control. Results are presented from a 180 nm CMOS integrated circuit prototype verified using in vivo experiments with a tungsten microwire array implanted in rodent cortex. The integrated circuit prototype achieves

This brief presents a design strategy for a neural recording amplifier array with ultralow-power low-noise operation that is suitable for large-scale integration. The topology combines a highly efficient but supply-sensitive single-ended first stage with a shared reference channel and a differential second stage to effect feedforward supply noise cancellation, combining the low power of single-ended amplifiers with improved supply rejection. For a two-channel amplifier, the measurements show a midband gain of 58.7 dB and a passband from 490 mHz to 10.5 kHz. The amplifier consumes 2.85 \mu\mboxA per channel from a 1-V supply and exhibits an input-referred noise of 3.04 \mu\mboxV_\mathrmrms from 0.1 Hz to 100 kHz, corresponding to a noise efficiency factor of 1.93. The power supply rejection ratio is better than 50 dB in the passband. The amplifier is fabricated in a 90-nm CMOS process and occupies 0.137 \mboxmm^2 of chip area. [ABSTRACT FROM AUTHOR]

We present a 320-channel active probe for high-spatial-resolution neuromonitoring and responsive neurostimulation. The probe comprises an integrated circuit (IC) cell array bonded to the back side of a pitch-matched microelectrode array. The IC enables up to 256-site neural recording and 64-site neural stimulation at the spatial resolution of 400 \mum and 200 \mum, respectively. It is suitable for direct integration with electrode arrays with the shank pitch of integer multiples of 200 \mum. In the presented configuration, the IC is bonded with a 8\,\times\,8 400 \mum-pitch Utah electrode array (UEA) and up to additional 192 recording channels are used for peripheral neuromonitoring. The 0.35 \mum CMOS circuit array has a total die size of 3.5 mm\,\times\,3.65 mm. Each stimulator channel employs a current memory for simultaneous multi-site neurostimulation, outputs 20 \muA–250 \muA square or arbitrary waveform current, occupies 0.02 mm^2, and dissipates 2.76 \muW quiescent power. Each fully differential recording channel has two stages of amplification and filtering and an 8-bit single-slope ADC, occupies 0.035 mm^2 , and consumes 51.9 \muW. The neural probe has been experimentally validated in epileptic seizure propagation studies in a mouse hippocampal slice in vitro and in responsive neurostimulation for seizure suppression in an acute epilepsy rat model in vivo . [ABSTRACT FROM PUBLISHER]

When designing an analog front-end for neural interfacing, it is hard to evaluate the interplay of priority features that one must upkeep. Given the competing nature of design requirements for such systems a good understanding of these trade-offs is necessary. Low power, chip size, noise control, gain, temporal resolution and safety are the salient ones. There is a need to expose theses critical features for high performance neural amplifiers as the density and performance needs of these systems increases. This review revisits the basic science behind the engineering problem of extracting neural signal from living tissue. A summary of architectures and topologies is then presented and illustrated through a rich set of examples based on the literature. A survey of existing systems is presented for comparison based on prevailing performance metrics. [ABSTRACT FROM AUTHOR]

A novel signal folding and reconstruction scheme for neural recording applications that exploits the 1/f^n characteristics of neural signals is described in this paper. The amplified output is ‘folded’ into a predefined range of voltages by using comparison and reset circuits along with the core amplifier. After this output signal is digitized and transmitted, a reconstruction algorithm can be applied in the digital domain to recover the amplified signal from the folded waveform. This scheme enables the use of an analog-to-digital convertor with less number of bits for the same effective dynamic range. It also reduces the transmission data rate of the recording chip. Both of these features allow power and area savings at the system level. Other advantages of the proposed topology are increased reliability due to the removal of pseudo-resistors, lower harmonic distortion and low-voltage operation. An analysis of the reconstruction error introduced by this scheme is presented along with a behavioral model to provide a quick estimate of the post reconstruction dynamic range. Measurement results from two different core amplifier designs in 65 nm and 180 nm CMOS processes are presented to prove the generality of the proposed scheme in the neural recording applications. Operating from a 1 V power supply, the amplifier in 180 nm CMOS has a gain of 54.2 dB, bandwidth of 5.7 kHz, input referred noise of 3.8 \mu Vrms and power dissipation of 2.52 \mu W leading to a NEF of 3.1 in spike band. It exhibits a dynamic range of 66 dB and maximum SNDR of 43 dB in LFP band. It also reduces system level power (by reducing the number of bits in the ADC by 2) as well as data rate to 80% of a conventional design. In vivo measurements validate the ability of this amplifier to simultaneously record spike and LFP signals. [ABSTRACT FROM PUBLISHER]

This paper reports on design and development of a reliable, single-chip, multichannel wireless biotelemetry microsystem intended for extracellular neural recording from awake, and behaving small animal models. The system requirements for reliable neural recording are identified and the inherently conflicting requirements of low power and reliability are addressed at architectural and circuit levels. The 2.85\,\times\,3.84 mm^2, mixed-signal ASIC is fabricated in a 0.5 \mum 2P3M n-well standard CMOS process; and integrates a low-noise front-end, programmable digital controller, an RF modulator, and an RF power amplifier at the ISM band of 433 MHz on a single-chip. The microsystem, incorporating the ASIC, features 9-channel, is programmable, weighs 2.2 g (including batteries) and has dimensions of 2.2\,\times \,1.1\,\times \,0.5 cm^3. The transmitter consumes 5 mW and has a measured input referred voltage noise of 4.58 \mu V rms, 6.20 \mu V rms, and 7.81 \mu V rms at transmission distances of 3 m, 10 m, and 20 m, respectively. The measured inter-channel crosstalk is less than 3.5% and battery life is about an hour. The presented biotelemetry system has been successfully used in two in-vivo neural recording experiments: i) from the antennas of a freely roaming South-American cockroach, and ii) from the hippocampus of an awake and mobile rat. [ABSTRACT FROM PUBLISHER]

Neural probes have become the most important tool for enabling neuroscientists to place microelectrode sensors close to individual neurons and to monitor their activity in vivo. With such devices, it is possible to perform acute or chronic extracellular recordings of electrical activity from a single neuron or from groups of neurons. After the many developments in neural implants, it has become clear that large arrays of electrodes are desirable to further investigate the activity performed by complex neural networks. Therefore, in this paper, we propose a CMOS neural probe containing 455 active electrodes in the probe shank (100 \mum wide, 10 mm long, and 50 \mum thick) and 52 simultaneous readout channels in the probe body (2.9\,\times\,3.3 mm^2). In situ amplification under each electrode enables low-impedance interconnection lines, regardless of the electrode impedance, with a residual crosstalk of -44.8 dB. This design has been implemented in a 0.18-\mum standard CMOS technology, with additional CMOS-compatible post-processing performed at wafer level to define the electrodes and the probe outline. In this architecture, the analog front-end achieves an input-referred noise of 3.2 \mu \Vrms and an NEF of 3.08. The power consumption of the core circuit is 949.8 \muW, while the total power consumption is 1.45 mW. The high-density active-electrode array in this neural probe allows for the massive recording of neural activity. In vivo measurements demonstrate successful simultaneous recordings from many individual cells. [ABSTRACT FROM PUBLISHER]

This paper presents a digital neural/EMG telemetry system small enough and lightweight enough to permit recording from insects in flight. It has a measured flight package mass of only 38 mg. This system includes a single-chip telemetry integrated circuit (IC) employing RF power harvesting for battery-free operation, with communication via modulated backscatter in the UHF (902–928 MHz) band. An on-chip 11-bit ADC digitizes 10 neural channels with a sampling rate of 26.1 kSps and 4 EMG channels at 1.63 kSps, and telemeters this data wirelessly to a base station. The companion base station transceiver includes an RF transmitter of +36 dBm (4 W) output power to wirelessly power the telemetry IC, and a digital receiver with a sensitivity of -70 dBm for 10^-5 BER at 5.0 Mbps to receive the data stream from the telemetry IC. The telemetry chip was fabricated in a commercial 0.35 \mum 4M1P (4 metal, 1 poly) CMOS process. The die measures 2.36\,\times\,1.88 mm, is 250 \mum thick, and is wire bonded into a flex circuit assembly measuring 4.6\,\times\,6.8 mm. [ABSTRACT FROM PUBLISHER]

Rapid development in miniature implantable electronics are expediting advances in neuroscience by allowing observation and control of neural activities. The first stage of an implantable biosignal recording system, a low-noise biopotential amplifier (BPA), is critical to the overall power and noise performance of the system. In order to integrate a large number of front-end amplifiers in multichannel implantable systems, the power consumption of each amplifier must be minimized. This paper introduces a closed-loop complementary-input amplifier, which has a bandwidth of 0.05 Hz to 10.5 kHz, an input-referred noise of 2.2 \muVrms, and a power dissipation of 12 \muW. As a point of comparison, a standard telescopic-cascode closed-loop amplifier with a 0.4 Hz to 8.5 kHz bandwidth, input-referred noise of 3.2 \muVrms, and power dissipation of 12.5 \muW is presented. Also for comparison, we show results from an open-loop complementary-input amplifier that exhibits an input-referred noise of 3.6 \muVrms while consuming 800 nW of power. The two closed-loop amplifiers are fabricated in a 0.13 \mum CMOS process. The open-loop amplifier is fabricated in a 0.5 \mum SOI-BiCMOS process. All three amplifiers operate with a 1 V supply. [ABSTRACT FROM PUBLISHER]

This paper describes a micropower low-noise neural front-end circuit capable of recording epileptic fast ripples (FR). The front-end circuit consisting of a preamplifier followed by a 6th-order bandpass filter is designed for signal sensing in a future epileptic deep brain stimulator. A current-splitting technique is combined with an output-branch current scaling technique in a folded-cascode amplifier structure to improve the noise and power tradeoff in the preamplifier. In measurements, the preamplifier exhibits 39.4 dB DC gain, 0.36 Hz to 1.3 kHz of -3 dB bandwidth, and 3.07 \muVrms total input-referred noise while consuming 2.4 \muW from a 2.8 V power supply provided by an on-chip regulator circuit. A noise efficiency factor (NEF) of 3.09 is achieved with minimal power consumption and is one of the lowest published to date. The 6th-order follow-the-leader feedback elliptic bandpass filter passes FR signals and provides -110 dB/decade attenuation to out-of-band frequency components. In measurements, the entire front-end circuit achieves a mid-band gain of 38.5 dB, a bandwidth from 250 to 486 Hz, and a total input-referred noise of 2.48 \muVrms while consuming 4.5 \muW from the 2.8 V power supply. The front-end NEF achieved is 7.6. To the authors' knowledge, the proposed epileptic seizure- detection system is the first to achieve the FR-recording functionality. The chip is fabricated in a standard 0.6 \mum CMOS process. Die size is 0.45 mm^2. [ABSTRACT FROM AUTHOR]

We have developed miniature telemetry systems that capture neural, EMG, and acceleration signals from a freely moving insect or other small animal and transmit the data wirelessly to a remote digital receiver. The systems are based on custom low-power integrated circuits (ICs) that amplify, filter, and digitize four biopotential signals using low-noise circuits. One of the chips also digitizes three acceleration signals from an off-chip microelectromechanical-system accelerometer. All information is transmitted over a wireless \sim 900-MHz telemetry link. The first unit, using a custom chip fabricated in a 0.6-\mum BiCMOS process, weighs 0.79 g and runs for two hours on two small batteries. We have used this system to monitor neural and EMG signals in jumping and flying locusts as well as transdermal potentials in weakly swimming electric fish. The second unit, using a custom chip fabricated in a 0.35-\mum complementary metal–oxide semiconductor CMOS process, weighs 0.17 g and runs for five hours on a single 1.5-V battery. This system has been used to monitor neural potentials in untethered perching dragonflies. [ABSTRACT FROM PUBLISHER]

Abstract: This paper seeks to elucidate the design and implementation of an instrumentation amplifier, filters, LabVIEW-based spike detection, and automatic spike counting to detect pleasure sensation in the rat using invasive BCI. This method involved sites related to pleasure, and after acquiring signals from the ventral pallidum, facial motor cortex, and orbitofrontal cortex, these signals were analyzed to assess the pleasure sensation in the rat. The results illustrated a decreased spike rate in the motor and orbitofrontal cortices and an increased spike rate in the ventral pallidum during pleasure. The pleasure detection experiment was conducted four times to obtain the mean values of spike rates. The motor cortex had 9spikes/s, the orbitofrontal cortex had 18spikes/s and the ventral pallidum had 34spikes/s. The correlation coefficient is above 78%, effectiveness of the experiment. [ABSTRACT FROM AUTHOR]

To create a wireless neural recording system that can benefit from the continuous advancements being made in embedded microcontroller and communications technologies, an embedded-system-based architecture for wireless neural recording has been designed, fabricated, and tested. The system consists of commercial-off-the-shelf wireless-enabled processor modules (motes) for communicating the neural signals, and a back-end database server and client application for archiving and browsing the neural signals. A neural-signal-acquisition application has been developed to enable the mote to either acquire neural signals at a rate of 4000 12-bit samples per second, or detect and transmit spike heights and widths sampled at a rate of 16670 12-bit samples per second on a single channel. The motes acquire neural signals via a custom low-noise neural-signal amplifier with adjustable gain and high-pass corner frequency that has been designed, and fabricated in a 1.5- µm CMOS process. In addition to browsing acquired neural data, the client application enables the user to remotely toggle modes of operation (real-time or spike-only), as well as amplifier gain and high-pass corner frequency. [ABSTRACT FROM AUTHOR]

A 3D microsystem for multi-site penetrating extracellular neural recording from the brain is presented. A 16 x 16-channel neural recording interface integrated prototype fabricated in 0.35 μm CMOS occupies 3.5 mm x 4.5 mm area. Each recording channel dissipates 15 W of power with input-referred noise of 7 μVrms over 5 kHz bandwidth. A switched-capacitor delta read-out data compression circuit trades recording accuracy for the output data rate. An array of 1.5 mm platinum-coated microelectrodes is bonded directly onto the die. Results of in vitro experimental recordings from intact mouse hippocampus validate the circuit design and the on-chip electrode bonding technology. [ABSTRACT FROM AUTHOR]

This paper describes an amplification and spectral processing IC for extracting key bioelectrical signals, or "biomarkers", which are expressed in the brain's field potentials. The intent is to explore using these biomarkers to drive prosthetic actuators or titrate therapy devices such as a deep-brain neurostimulator. The prototype IC uses 5 $mu{hbox{W}}$/channel to resolve signals on the order of 1 μVrms. The four channels on the device provide independent spectral analysis from DC to 1 kHz, with variable bandwidth and power filtering characteristics. The noise floor and flexible spectral processing support a broad range of potential applications including sleep staging, Parkinson's disease, detection of movement intention for neuroprosthesis, and detection of high frequency "fast ripples" for exploring seizure prediction. To fully demonstrate the IC's functionality, we include results from a prototype "closed-loop" neurostimulator implementing adaptive titration of therapy based on measured field potential activity. [ABSTRACT FROM AUTHOR]

A 256-channel integrated interface for simultaneous recording of distributed neural activity from acute brain slices is presented. An array of 16 times 16 Au recording electrodes are fabricated directly on the die. Each channel implements differential voltage acquisition, amplification and band-pass filtering. In-channel analog memory stores an electronic image of neural activity. A 3 mm times 4.5 mm integrated prototype fabricated in a 0.35-mum CMOS technology is experimentally validated in single-channel extracellular in vitro recordings from the hippocampus of mice and in multichannel simultaneous recordings in a controlled environment [ABSTRACT FROM PUBLISHER]

A mixed-signal front-end processor for multichannel neuronal recording is described. It receives 12 differential-input channels of implanted recording electrodes. A programmable cutoff High Pass Filter (HPF) blocks dc and low-frequency input drift at about 1 Hz. The signals are band-split at about 200 Hz to low-frequency Local Field Potential (LFP) and high-frequency spike data (SPK), which is band limited by a programmable-cutoff LPF, in a range of 8-13 kHz. Amplifier offsets are compensated by 5-bit calibration digital-to-analog converters (DACs). The SPK and LFP channels provide variable amplification rates of up to 5000 and 500, respectively. The analog signals are converted into 10-bit digital form, and streamed out over a serial digital bus at up to 8 Mbps. A threshold filter suppresses inactive portions of the signal and emits only spike segments of programmable length. A prototype has been fabricated on a 0.35-µm CMOS process and tested successfully, demonstrating a 3-µV noise level. Special interface system incorporating an embedded CPU core in a programmable logic device accompanied by real-time software has been developed to allow connectivity to a computer host. [ABSTRACT FROM AUTHOR]

Recent work in field of neuroprosthetics has demonstrated that by observing the simultaneous activity of many neurons in specific regions of the brain, it is possible to produce control signals that allow animals or humans to drive cursors or prosthetic limbs directly through thoughts. As neuroprosthetic devices transition from experimental to clinical use, there is a need for fully-implantable amplification and telemetry electronics in close proximity to the recording sites. To address these needs, we developed a prototype integrated circuit for wireless neural recording from a 100-channel microelectrode array. The design of both the system-level architecture and the individual circuits were driven by severe power constraints for small implantable devices; chronically heating tissue by only a few degrees Celsius leads to cell death. Due to the high data rate produced by 100 neural signals, the system must perform data reduction as well. We use a combination of a low-power ADC and an array of "spike detectors" to reduce the transmitted data rate while preserving critical information. The complete system receives power and commands (at 6.5 kb/s) wirelessly over a 2.64-MHz inductive link and transmits neural data back at a data rate of 330 kb/s using a fully-integrated 433-MHz FSK transmitter. The 4.7 × 5.9 mm² chip was fabricated in a 0.5-µm 3M2P CMOS process and consumes 13.5 mW of power. While cross-chip interference limits performance in single-chip operation, a two-chip system was used to record neural signals from a Utah Electrode Array in cat cortex and transmit the digitized signals wirelessly to a receiver. [ABSTRACT FROM AUTHOR]

There is a need among scientists and clinicians for low-noise low-power biosignal amplifiers capable of amplifying signals in the millihertz-to-kilohertz range while rejecting large dc offsets generated at the electrode-tissue interface. The advent of fully implantable multielectrode arrays has created the need for fully integrated micropower amplifiers. We designed and tested a novel bioamplifier that uses a MOS-bipolar pseudoresistor element to amplify low-frequency signals down to the millihertz range while rejecting large dc offsets. We derive the theoretical noise-power tradeoff limit - the noise efficiency factor - for this amplifier and demonstrate that our VLSI implementation approaches this limit by selectively operating MOS transistors in either weak or strong inversion. The resulting amplifier, built in a standard 1.5-μm CMOS process, passes signals from 0.025Hz to 7.2 kHz with an input-referred noise of 2.2 μVrms and a power dissipation of 80 μW while consuming 0.16 mm2 of chip area. Our design technique was also used to develop an electroencephalogram amplifier having a bandwidth of 30 Hz and a power dissipation of 0.9 μW while maintaining a similar noise-power tradeoff. [ABSTRACT FROM PUBLISHER]