1. Upset-like fault injection in VHDL descriptions: A method and preliminary results
- Author
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O. Calvo, Raoul Velazco, Regis Leveugle, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Universidad Nacional de Córdoba [Argentina], Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)
- Subjects
single-event-upset-phenomena ,Computer science ,02 engineering and technology ,01 natural sciences ,Fuzzy logic ,bit-flip-simulation ,Upset ,Computer Science::Hardware Architecture ,High-level synthesis ,0103 physical sciences ,VHDL ,0202 electrical engineering, electronic engineering, information engineering ,high-level-circuit-description ,ground-testing ,[SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics ,computer.programming_language ,natural-radiation-interaction ,010308 nuclear & particles physics ,business.industry ,upset-like-fault-injection ,020208 electrical & electronic engineering ,Hardware description language ,space-environment ,VHDL-descriptions ,memory-cells ,Fault injection ,Single event upset ,Embedded system ,PACS 85.42 ,business ,computer ,Space environment - Abstract
Investigates an approach allowing one to evaluate the consequences of single event upset phenomena for the reliable operation of processors. The method is based on the simulation of bit flips using a modified version of a high-level circuit description. Preliminary results illustrate the potential of this new strategy.
- Published
- 2001
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