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Upset-like fault injection in VHDL descriptions: A method and preliminary results
- Source :
- Proceedings-2001-IEEE-International-Symposium-on-Defect-and-Fault-Tolerance-in-VLSI-Systems., DFT
- Publication Year :
- 2001
- Publisher :
- HAL CCSD, 2001.
-
Abstract
- Investigates an approach allowing one to evaluate the consequences of single event upset phenomena for the reliable operation of processors. The method is based on the simulation of bit flips using a modified version of a high-level circuit description. Preliminary results illustrate the potential of this new strategy.
- Subjects :
- single-event-upset-phenomena
Computer science
02 engineering and technology
01 natural sciences
Fuzzy logic
bit-flip-simulation
Upset
Computer Science::Hardware Architecture
High-level synthesis
0103 physical sciences
VHDL
0202 electrical engineering, electronic engineering, information engineering
high-level-circuit-description
ground-testing
[SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
computer.programming_language
natural-radiation-interaction
010308 nuclear & particles physics
business.industry
upset-like-fault-injection
020208 electrical & electronic engineering
Hardware description language
space-environment
VHDL-descriptions
memory-cells
Fault injection
Single event upset
Embedded system
PACS 85.42
business
computer
Space environment
Subjects
Details
- Language :
- English
- Database :
- OpenAIRE
- Journal :
- Proceedings-2001-IEEE-International-Symposium-on-Defect-and-Fault-Tolerance-in-VLSI-Systems., DFT
- Accession number :
- edsair.doi.dedup.....1503840c02cf053f81fafc3eaaaa662f
- Full Text :
- https://doi.org/10.1109/DFTVS.2001.966778⟩