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This work presents an analytical model for the drain and gate currents of silicon nanowire and nanosheet MOS transistors valid in all operating regions in the temperature range from 300 to 500 K. Analytical models for the tunneling components as well as for the reversely biased drain‐to‐channel PN junction are presented. Also, the models accounting for the necessary modifications in the silicon physical quantities for high‐temperature operation, such as the maximum carrier mobility, the bandgap, and the intrinsic carrier concentration, are presented. The proposed model uses a single set of parameters, extracted at room temperature, to describe the high‐temperature operation of silicon nanowire MOSFETs. The model is validated with comparisons between modeled and experimental results for devices with different fin widths and operating temperatures, with good agreement. [ABSTRACT FROM AUTHOR]

Two-dimensional rhenium disulfide (ReS2), a member of the transition-metal dichalcogenide family, has received significant attention due to its potential applications in field-effect transistors (FETs), photodetectors, and memories. In this work, we investigate the suppression of the subthreshold current during the forward voltage gate sweep, leading to an inversion of the hysteresis in the transfer characteristics of ReS2 nanosheet-based FETs from clockwise to anticlockwise. We explore the impact of temperature, sweeping gate voltage, and pressure on this behavior. Notably, the suppression in current within the subthreshold region coincides with a peak in gate current, which increases beyond a specific temperature but remains unaffected by pressure. We attribute both the suppression in drain current and the presence of peak in gate current to the charge/discharge process of gate oxide traps by thermal-assisted tunnelling. The suppression of the subthreshold current at high temperatures not only reduces power consumption but also extends the operational temperature range of ReS2 nanosheet-based FETs. [ABSTRACT FROM AUTHOR]

For improving self-heating effects (SHEs) in gate-all-around metal-oxide-semiconductor field-effect transistors (GAA MOSFETs), hetero-gate-dielectric (HGD) is utilized. The HGD consists of hafnium dioxide (HfO2) and silicon dioxide (SiO2), which has high thermal conductivity, hence SHEs are improved. In order to validate the HGD, technology computer-aided design (TCAD) simulation is performed through Synopsys Sentaurus three-dimensional (3D) tool. As a result, when the HGD is adopted in GAA MOSFETs, SHEs can be significantly improved from 498 K to 415 K. In addition, suppression of gate current, more than 2 orders, is also achieved because of bigger bandgap of SiO2 in HGD. Consequently, this structure takes advantage of higher thermal conductivity and bigger bandgap of SiO2, and higher permittivity of HfO2 for improving SHEs and gate leakage current.

The gate leakage current of p-GaN gate HEMTs is modeled based on surface potential calculations. The model accurately describes the bias and temperature dependence of the gate leakage. Thermionic emission is the main mechanism of the gate current in forward bias operation while hopping transport component is the main mechanism of gate current in reverse bias operation. This newly developed gate current model was implemented in Verilog-A. A good agreement between the simulations and experimental data demonstrates the accuracy of the model. [ABSTRACT FROM AUTHOR]

The hot carrier (HC) induced degradation has become a major concern in advanced CMOS technologies because of non-scalable $\text{V}_{\mathrm{ DD}}$. In this work, we have shown that the HC induced degradation in gate-first HKMG nMOS transistors can be modulated by optimizing the device width, lanthanum capping layer thickness, and pre-gate carbon (C) implant. The physics responsible for these observations are investigated and attributed to the reduction in the number of defects (traps) in hafnium oxide (HfO2) and reduction in carrier injection into these defects. It is also shown that the HC performance of these transistors could be further improved by increasing the active-to-active spacing. [ABSTRACT FROM AUTHOR]

The gate leakage current is analytically modeled for AlInN/GaN and AlGaN/GaN high-electron mobility transistor (HEMT) devices using a charge-based approach. Four different current mechanisms, namely Fowler–Nordheim tunneling (FNT), Poole–Frenkel emission (PFE), thermionic emission (TE), and defect-assisted tunneling (DAT) are considered. FNT and PFE are two dominant mechanisms in the reverse bias region, while TE and DAT are significant in forward and near zero gate bias regions, respectively. This model is implemented in Verilog-A and validated by comparison with experimental data for both AlInN/GaN and AlGaN/GaN HEMTs. It is shown that the model is able to capture the effects of Al molar fraction, barrier thickness, and temperature on gate leakage current over a wide range of gate and drain voltages. [ABSTRACT FROM AUTHOR]

This paper describes a compact model for a silicon-carbide (SiC) MOSFET, which features both characterization and modeling of a new drain-gate capacitor. In addition, the internal gate resistance and the internal stray inductances of the discrete package are experimentally evaluated and modeled by a newly-proposed method. The gate drive circuit is also modeled and involved in this simulation. The comprehensive modeling procedure is also considered, which offers an efficient modeling process. The model shows excellent agreements in transient behavior of both gate drive circuit and main power circuit between experimental and simulated waveforms. The comparison shows accurate reproducibility of a rate of drain-source voltage change and a rate of drain-current change within an error of 15%, which could not be realized with the conventional stray capacitance models. This successful validation indicates that the developed model would offer a new modeling concept and be expected to open up the possibilities of the simulation study for evaluating and designing detailed performance of SiC-MOSFETs. [ABSTRACT FROM PUBLISHER]

• Thinner or high-permittivity dielectrics in organic transistors result in lower threshold voltages. • Crosslinked polyvinyl alcohol (PVA) has better insulation properties and stiffer structure. • Polymer gate dielectrics have gate voltage hysteresis, causing device parameter variation. • Mobile charges in PVA come from sodium in PVA hydrolysis. • This work studies Al-PVA-Si capacitors to optimize PVA's dielectric characteristics. This article discusses the use of polyvinyl alcohol (PVA) as a dielectric in Organic Field Effect Transistors. PVA is a promising candidate for use as a dielectric due to its flexibility, high dielectric constant, and high resistivity, as well as its solubility in water, low cost, wide commercial availability, non-toxicity, and versatility. The article explores different regimes of PVA layer preparation and their effects on the dielectric characteristics of metal-PVA-silicon capacitors. The study analyzes the parameters of previous purification of PVA, crosslinking, and spin coating deposition velocity of PVA solutions. The article also investigates gate voltage hysteresis with PVA as a gate dielectric and the causes of mobile charges that can interfere with the performance of the dielectric. The study aims to optimize the dielectric characteristics of PVA and discover the best parameters for PVA use in electronic applications. [ABSTRACT FROM AUTHOR]

In this paper, we based on the gate structure of p-GaN HEMT connected with Schottky diode and PIN diode and analyzed the threshold voltage shift mechanism under the influence of gate voltage. Based on the carrier transport mechanism, the electron injection current and hole injection current of the p-GaN layer is discussed and calculated, while the gate current model and threshold voltage shift model of the p-GaN HEMT are analyzed. The accuracy of the model is verified by comparing with the experimental data. The effects of p-GaN doping concentration, AlGaN barrier layer thickness and Al component on the gate current and V TH shift are discussed based on the model. By optimizing the device structure and process parameters, the gate current of HEMT can be reduced and the stability of V TH can be improved. • The effect of electron injection and hole injection in the p-GaN layer on the threshold voltage shift is discussed and analyzed. • The threshold voltage shift and gate current are modeled. The threshold voltage shift and gate current are modeled, and the effects of device structure parameters on them are discussed. • Based on the developed model, the optimization of the device structure design is discussed. The model can provide guidance for the device structure design. [ABSTRACT FROM AUTHOR]

This paper discusses in detail the effects of transistor width, layout, and technological parameters like gate dielectric and Lanthanum capping layer thickness on positive bias temperature instability (PBTI) of nMOS transistors fabricated using 28-nm gate-first High- K metal gate CMOS technology. It is shown that the PBTI reduces with decrease in width ( W ), increase in capping layer thickness and decrease in high- K dielectric thickness. The physical mechanisms responsible for these dependencies are investigated and attributed to the modulation of preexisting traps in the high- K dielectric and the modulation of electron injection into these traps. It is also shown that the PBTI of the devices could be improved by dividing a single active into multiple actives, by increasing active-to-active spacing and gate pitch. [ABSTRACT FROM PUBLISHER]

2D TCAD Sentaurus simulations based on Drift-Diffusion transport are performed to identify the modeling parameters that crucially affect the reliability characteristics of AlGaN/GaN HEMT devices, demonstrated by their effects on the gate leakage characteristic. The behavioural nature and impact of each parameter on the leakage performance is discussed. Schottky gate tunneling and trapping effects within the structure are two major reliability issues that modulate the leakage characteristic. Hence, their contributions are precisely modeled. A simulation methodology is presented to recognize the relative control of individual parameters on distinct regions of the leakage characteristic. This modeling approach is demonstrated for a GaN HEMT technology and can be further applied to facilitate reliability comparisons across different device technologies. This validates TCAD simulation to be an effective aiding tool in reviewing and interpreting GaN HEMT reliability performance and design choices. [ABSTRACT FROM AUTHOR]